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<qu1j0t3> did AWS not have a product like this already?
<sorear> aws gives you vivado as a service
<sorear> it’s plausibly competing with vivado node licenses, but it’s not in any sense competing with vivado or hdls per se
<sorear> aws docs talk about opencl hls, but I’m assuming? that’s a stock vivado feature
<TD-Linux> this whole thing seems just like vivado hls with a "slick" skin
<TD-Linux> and by slick I mean 20GB of Java
<hackerfoo> It seems like Intel is doing something similar with SYCL/One API.
<hackerfoo> I think it's really because of the interest in accelerators and the success of GPGPU.
<hackerfoo> It probably doesn't change things much for people already using FPGAs.
<freemint> Yeah that would be to easy
<kc8apf> Devs: FPGAs are too hard to program
<kc8apf> Devs: no. That's horribly slow. I want more helpful tools and language for hardware.
<kc8apf> Devs: *grumble*
<kc8apf> Xilinx/Intel: oh? You want to program it in C?
<kc8apf> Xilinx/Intel: got it! Now you can use OpenCL!
<kc8apf> Xilinx/Intel: shiny, new UI with a library to hide all the ugly hardware bits
<kc8apf> Devs: seriously?!?! We just want fewer foot guns!
<hackerfoo> Xilinx/Intel: But TensorFlow!!!
<hackerfoo> Our FPGAs practically program themselves! (given a million labeled positive and negative examples)
<sorear> isn’t all this being pushed by managers who are “what if we could do massively parallel computing without paying market rates for people who know parallel languages”
<whitequark> lol
<tpw_rules> i mean tbf i don't want to figure out how to write a matrix multiplication engine in my fpga
<freemint> I think the sole purpose of this move is to sell to a new market
<tpw_rules> and make accelerators "easy"
<freemint> believe me if they could make more money by making it harder they would do that.
<whitequark> lol
<freemint> I wouldn't be supprised if they make programming FPGAs via these tool chains harder over time.
<cr1901_modern> Reminds me of that one fake C++ interview with Bjarne where he "admitted" C++ was designed to be difficult to artificially inflate dev salaries.
<hackerfoo> I want better tools so I can make cooler stuff.
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<gregdavill> I'm trying to move a ECP5 project from Diamond to Trellis. I'm using the ECLK-BRIDGE blocks as I've got a DDR3 design spread across two sides.
<gregdavill> It looks like ECLKBRIDGECS is not a block available in trellis....
<daveshah> I'm afraid it's not fully supported yet. Best bet is to remove it
<daveshah> Trellis allows some kinds of clock routing that Diamond doesn't but usually work
<gregdavill> Ahh okay, thanks! I'll see if I can get it working without.
<GenTooMan> hackerfoo the only problem I foresee with making "cooler" stuff is the relative definition of cool. Better tools however does make it easier to do things regardless of that.
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<hackerfoo> Here's the design of the bus that I'm using for arrays in Popr:
<hackerfoo> It's minimal, but I think it should be flexible enough.
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<hackerfoo> There's no arbitration because only one reader/writer can be active at a time.
<emily> gosh verilog seems like an unpleasant compilation target
<hackerfoo> The interesting parts are: ready/valid applies only to signals into the bus (addr, we, di), and all signals into the bus must be low when valid is low, allowing these signals to be OR'ed.
<hackerfoo> emily: It is, but I'm using macros to cope. SystemVerilog would probably be a lot better.
* emily is grateful for RTLIL
<hackerfoo> The output is still readable if you're familiar with the macros.
<hackerfoo> emily: I'm interested in RTLIL, but I don't want to be tied to Yosys. Is it a lot easier to work with? Can it be converted to reasonable Verilog?
<hackerfoo> I think I've solved all the major problems with generating Verilog by now. The biggest one was packaging bidirectional signals, and re-implementing `wor` since some tools (Vivado) won't synthesize that.
<hackerfoo> *biggest two
<emily> hackerfoo: Yosys can compile RTLIL to Verilog, which nMigen uses
<emily> the quality of the Verilog isn't as good as it could be because of being unfixed
<hackerfoo> emily: I guessed that, but I'd like it to be understandable e.g. good net names for simulation, writing testbenches, etc.
<emily> right. nMigen takes special effort to produce good names and the like
<emily> whitequark would know more about it than me (oMigen used Verilog as a compile target; AIUI switching to RTLIL made nMigen a lot simpler)
<emily> RTLIL is still "fairly" high level I'd say
<hackerfoo> It's funny that the IL is higher level than the input.
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<hackerfoo> (if that's the case, I haven't looked at it much)
<hackerfoo> It might be worth converting my macros into a custom preprocessor that others could use. Then the modified Verilog would be more readable. I currently have to use iverilog to expand the macros anyway.
<hackerfoo> Eh, it would just end up being another macro processor. Maybe I'll switch to m4.
<emily> well, I think RTLIL is definitely not as "high level" as Verilog, it's just that the high-level Verilog features are actually footguns
<emily> especially for a compiler backend
<hackerfoo> I see. My other target is C (and so it the implementation language), so I'm familiar with footguns.
<hackerfoo> I just use C as a high level SSA, so I'm using Verilog as the RTL equivalent, I guess.
<emily> *nods*
* emily has vaguely considered hacking on an RTLIL backend for Clash or something
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<blueCmd> Hello! I was wondering if somebody is working on MachXO reverse bitstream -> hdl?
<blueCmd> I have a motherboard with an CPLD I would like to see if I can modify a bit
<kc8apf> I recall cr1901_modern looking into MachXO. Last I heard it was on hold.
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<azonenberg> speaking of verilog/systemverilog things i got bit by recently
<azonenberg> apparently there's not strong typing on structs
<azonenberg> so if i have a struct foo in one module and i hook it up to a port of type struct bar
<azonenberg> there's no warning if they're the same size
<azonenberg> if foo and bar have a field with the same name, but at a different location, you will get very confused :p
<kc8apf> What? I really hope that's a bug rather than a spec omission
<azonenberg> This was with vivado, and it's POSSIBLE there was a warning i missed
<azonenberg> because vivado loves to spam out thousands of warnings that mean nothing, especially if you use any of their IP cores
<azonenberg> Whatever happened to "zero warnings required for code to be considered release-ready"
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<rombik_su> Good strategy may be to change severity for most obnoxious warning to infos
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<GenTooMan> azonenberg I can see that happening I didn't haven't anything go boom but verilog has no strong typing which made some things more difficult instead of easier.
<azonenberg> Yeah. Like, if i'm doing low level stuff with a logic[31:0] i just want bits
<azonenberg> but if i explicitly create a type, i expect a type
<azonenberg> Casting to a wire or bit vector should be transparent, but going from one type to another should warn
<azonenberg> is there a name for something like that?
<azonenberg> like, you have a wildcard type you can cast anything to/from without warnings, but strong types as well?
<azonenberg> 100% strong typing in a HDL would be annoying, because if you need to take a chunk of data and spit it into a serialized protocol you'd be casting constantly
<azonenberg> So i think having both "raw bits" and "strong typing" in the same language would be ideal
<pie_> emily: something something typeclasses? ^
<pie_> having an extreme urge to try to give good input and im just not equipped for it, nevermind *hides*
<emily> I'm unqualified to comment because I like explicit casts
<pie_> emily: thats what i was trying to expand on
<emily> Clash deals with the (de)serialization case by just having a typeclass for decodable/encodable into bit strings though, yeah
<pie_> and yeah i was wondering what clash does
<pie_> so i guess a question would be if you really need to cast an annoyingly large amount and what can be done about it?
<pie_> id argue for explicit casts if they arent semantic no-ops, i wouldnt want the compiler to accidentally do the wrong thing automatically, but maybe theres an alway-safe subset of casts...
<qu1j0t3> might be good to look at examples rather than trying to generalise
<pie_> yeah, im pulling things out of thin air here heh
<qu1j0t3> there are certainly ways to make them implicit and typesafe (scala) but i think this is why emily DOESN'T want to do that lol
<pie_> emily: does it sound like it mnight makes sense to construct user types by wrapping some underlying bits data type and just get bit operations for free
* emily concurs with "scala ... emily DOESN'T want"
<qu1j0t3> it was implicit
<emily> pie_: doing that implicitly without conversion kind of sucks in the case where there are some bit operations that will violate invariants of your type
<pie_> ok
<pie_> yeah i guess that makes sense
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<m_w> xobs: was there any more work done towards getting the USB mass storage support working on FOMU?
<m_w> we are thinking of making an ICE40 based badge for the next open hardware summit
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