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<OmniMancer> is there any practical difference between using a LUT in an FPGA as a logic function and using it as ROM?
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<rvense> there's neither practical nor theoretical difference as far as i know. luts are memories, no matter how simple the relation between the input and output codes.
<rvense> you could also do the inverse, right? for an n*m ROM, you just need an n-bit inverter and m n-bit ANDs, a bunch of wires, and a long sunday afternoon.
<OmniMancer> indeed
<OmniMancer> It just struck me as a bit odd that the Anlogic datasheet specifically mentions being able to use the LUTs as ROM
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<daveshah> I would argue that's the wrong way round - LUTs are small ROMs that happen to br useful for logic l
<daveshah> *be useful
<OmniMancer> daveshah: well the LUTs are technically small RAMs in an FPGA but...
<daveshah> From a synthesis/PnR point of view they are ROMs
<OmniMancer> but yes it just so happens that ROM can compute arbitrary boolean functions
<OmniMancer> the distributed RAM in FPGAs uses them as RAMs though?
<daveshah> Yes, this is true (but probably not all of them)
<OmniMancer> at least the mslices in Anlogic can supposedly be dualport ram, lut4 logic and can also use carry chains
<OmniMancer> daveshah: one difference from lattice is that in one block there are 2 mslices and 2 lslcies, where the mslices can be used as distributed ram and the lslices are lut5s
<OmniMancer> So there are separate carry chains for the mslices and lslices
<OmniMancer> so the fuzzing will need 2 different fuzzers for the two kinds at least, annoyingly
<OmniMancer> I found someone who set up a picorv32 on an Anlogic part and made a pnl file from it to discover what instance type exist in pnls
<ZirconiumX> ...I might steal that idea, actually.
<OmniMancer> hmm?
<ZirconiumX> It's a pretty good way of discovering routing options
<OmniMancer> Oh I didn't want it just for routing though
<OmniMancer> mostly for what the settings patterns are for actual logic
<ZirconiumX> I do, at least
<OmniMancer> since there are two different slice types, so wanted to generate templates
<OmniMancer> ZirconiumX: what are you looking at?
<ZirconiumX> I'm working on reverse-engineering the Cyclone V
<ZirconiumX> And I'm at the annoying stage of trying to work out routing
<ZirconiumX> I think I need to write a parser for the Quartus Routing Constraints File format
<ZirconiumX> It *would* be easier if I understood the format though
<OmniMancer> ZirconiumX: interesting, I suspect using some reasonably complicated designs if you can generate routing constraints from them might help understanding
<ZirconiumX> Yeah, Quartus has back-annotation
<ZirconiumX> Unfortunately it's filled with helpful point names like R3 and C6
<OmniMancer> are those row 3 and column 6?
<OmniMancer> I am not sure what the routing in the pnl file looks like either
<OmniMancer> it has nets which have routing pips it seems
<OmniMancer> daveshah: does the NCL format ever have literal 0s and 1s in the LUT init expression?
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<OmniMancer> Is there any use to having a flipflop with the clock input muxed to a constant 0 or 1?
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<OmniMancer> I have become even more confused about the lslices
<daveshah> OmniMancer: the only thing I can think of is initialising it to one value and then asynchronously resetting it once to the other
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<OmniMancer> daveshah: ah yes I suppose, the diagram in the datasheet shows each of the clock, clock enable and SR can be set to their out of tile inputs, the negation of the out of tile input or the constants 1 or 0
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<tnt> huh ... verilator doesn't even build out of the box ? :/
<tnt> nm ... their configure script is "special" ...
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<OmniMancer> unhelpful "special" configure scripts
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<OmniMancer> daveshah: the anlogic tools seem unwilling to generate a bitstream from a literally empty model, the lattice tools are happy to do this?
<daveshah> Yes, from an ncl file at least
<daveshah> The other option is to create a bitstream that doesn't use any of the tiles being fuzzed
<daveshah> eg a single IO drive high or low in a remote corner of the chip
<OmniMancer> its helpfully complains: "BIT-8204 ERROR: Bitgen: top model is NULL."
<OmniMancer> I will see what I can get it to be happy with
<OmniMancer> It is happy if I give it the instance of it's config settings
<OmniMancer> which configure the programming pin behaviour after configuration I think
<OmniMancer> Though it does seem the empty bit stream contains no bits set to 1 (if I change the two settings in the config block to disabled)
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<goran-mahovlic> I can just say sorry that I cannot be here more often, but there are some clues that I could free my self from daytime job and work more with FPGA. And now I am here to announce that we have finally created subscribe page for ULX3S on CrowdSupply https://www.crowdsupply.com/radiona/ulx3s
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<davidthings> goran-mahovlic: subscribed!
<davidthings> I think I am going to be able to get my client to use the ULX3S for prototyping new devices. My first FPGA paid gig!
<OmniMancer> daveshah: is the project trellis DB implemented in C++ to handle deduplication?
<daveshah> Yes, the performance works out a bit better than Python
<daveshah> ecppack etc is faster and simpler to distribute in C++ than Python too
<OmniMancer> Indeed
<OmniMancer> I have hacked together something clumsier for current purposes
<OmniMancer> at some point I think a similar system will be needed
<OmniMancer> I have acquired some LUT init bit locations
<OmniMancer> I am now going to see if I can harvest such info for the whole grid of the device I am interested in, this will take some time
<goran-mahovlic> davidthing: Tnx! Actually project that will give some funds is great prototype that would combine ECP5 , power supply and ScopeIO for start https://www.crowdsupply.com/envox/eez-bb3
<goran-mahovlic> But possibilities are endless
<goran-mahovlic> We should have results ready in few days -- we want people to see that using prototyping new devices is cool!
<tnt> goran-mahovlic: could of questions: What resolution have you pushed the hdmi to ? And what frequency is the sdram ?
<goran-mahovlic> <daveshah> Do you have one picture that is listing all opensource tools with names of involved, probably on some of your presentation so I can steal it? I need it for Dublin presentation...
<goran-mahovlic> tnt: just a sec I need to check -- I know EMARD has some memtest where we was trying to get maximum speed for SDRAM, will check what he reported...
<goran-mahovlic> As for HDMI - think that davidshah knows best, but will check with EMARD also...
<tnt> I'm actually a bit surprised at the choice of SDRAM vs DDR. (I mean DDR1, not DDR2-3-4 that are harder to drive, but DDR1 is pretty much just SDR with half the clock rate and using both edges AFAIR)
<goran-mahovlic> It is just because of games
<goran-mahovlic> check Mister
<goran-mahovlic> or any other games board
<goran-mahovlic> we wanted to stay compatible with games, that was key reason
<tnt> ok, I see.
<goran-mahovlic> I think Mister board has DDR3, and SDRAM extension pcb
<daveshah> tnt: I've got up to 1080p30 working
<daveshah> 1080p60 is way beyond the rating of the IO
<daveshah> goran-mahovlic: yeah, let me find it
<tnt> daveshah: ok, so that's be ~ 350MHz DDR if my math is correct.
<daveshah> goran-mahovlic: see p3 of ds0.me/orconf19.odp
<daveshah> tnt: yup
<daveshah> ECP5 IO are limited to 800Mbps/400MHz
<goran-mahovlic> so probably 220MHz is what EMARD got as standard
<goran-mahovlic> I will find source if you have some board that you want to test?
<tnt> Don't have a board yet.
<goran-mahovlic> tnt: Do you want to test ULX3S I am sending package to gojimmypi if you will be at superconference?
<tnt> goran-mahovlic: I will be at superconf yes. But gojimmypi already said he would have "a gift" for me there :)
<goran-mahovlic> Yes, empty board :) I will include 12F :)
<goran-mahovlic> I do not have better one currently but I think you can put amazing things in 24K :)
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<tnt> goran-mahovlic: do they come with stencil ? :)
<goran-mahovlic> no, I do not have stencil -- I have only one that I use
<goran-mahovlic> 12F is already in package, along with bare PCB
<tnt> tx :) Do you have a link to the gerbers (of that exact board, not sure if there are revisions or smth) so I can have a stencil made ?
<goran-mahovlic> yes, just a sec that is 3.0.7 -- just before ADC filter
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<goran-mahovlic> This one is with ESP32
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<GoranMahovlic> Use this one if you will not use ESP32 https://github.com/emard/ulx3s/commit/bf74876beec80e790caf4f5d9ad87f7df1c252b6
<GoranMahovlic> but recheck (esp32 hole existence on the one you want) before sending to production
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<GoranMahovlic77> https://kitspace.org/boards/github.com/emard/ulx3s/ We are usually using this for parts ordering -- parts did not change a lot ...
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<goran-mahovlic> daveshah: tnx! Will use that one :)
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