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<daveshah>
emily: thanks, fixed (not sure yet why CI didn't pick it up)
<ZirconiumX>
whitequark: So, for the sake of discussion, what would it take to add interrupts of some kind to Boneless? You'd need to preserve and restore flags, W, PC; what else?
<ZirconiumX>
You'd also need to modify the state machine a bit, but I'll handwave that for now
<emily>
daveshah: yay, thanks!
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<azonenberg>
emily: i gave you my old Rigol a while ago, right? Or am i mixing you up with somebody else
<emily>
the latter, unless I've misplaced and then completely forgotten about it
<azonenberg>
lol ok, i must be confused then. It was somebody in one of the channels i hang out in
<azonenberg>
and the nick was a typically-female first name
<azonenberg>
i was just going to check in and ask how it was working out, but clearly i have the wrong person :)
<emily>
I mean hey, feel free to send one :p
<azonenberg>
Lol :p
<azonenberg>
trust me if i had any other test equipment to get rid of i'd be advertising it here
<azonenberg>
i am, actually, looking to unload a stereo microscope in the not too distant future ideally to someone Seattle based but i'd be willing to ship to anywhere in CONUS
<azonenberg>
Not for free, but at a fair discount vs MSRP
<azonenberg>
the only thing wrong with it is the design is annoying, in order to turn on the camera port you have to move a mirror that disables the left eyepiece
<azonenberg>
there's no beamsplitter
<azonenberg>
But if you aren't using it with a camera, or are OK with switching between "use the scope" and "take pictures with the scope" mode and not filming live while you work, that's not a problem
<azonenberg>
used for only like 2 weeks, mostly in original manufacturer packaging
<azonenberg>
but since it's a hodgepodge of two manufacturer SKUs (i swapped the stand out with a different one) i can't RMA it
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<ZirconiumX>
tpw_rules: Your docs have a bug; CMP's assembly listing is "CMP Rd, Ra, Rb", except that CMP has no destination register
<ZirconiumX>
Same for CMPI
<tpw_rules>
oh, i didn't notice that
<ZirconiumX>
Also, you still have JO instead of JV
<ZirconiumX>
And a merge conflict :P
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<OmniMancer>
how are gowin devices for open source tools?
<tnt>
OmniMancer: not supported yet by a full flow.
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<tnt>
I think yosys has some stuff. But no pnr flow.
<ZirconiumX>
tpw_rules: Also possibly worth remarking is that JSGT and JUGT have the same encoding
<ZirconiumX>
Same for JSLE/JULE
<OmniMancer>
tnt: Thanks
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<whitequark>
wait, what?
<whitequark>
they do not
<whitequark>
see manual/design.ods for encoding
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<balrog>
dang, USB4 spec is available
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<gruetzkopf>
AAAAAAAH
<gruetzkopf>
this has nothing to do with conventional usb?
<gruetzkopf>
with usb3-over-usb4 tunneling and all that
<gruetzkopf>
(and this time with FEC)
<whitequark>
yeah it doesn't include anything about USB2
<whitequark>
I think USB2 is basically totally separate at this point
<balrog>
whitequark: USB2 has been separate since USB3
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<whitequark>
yes, but they stopped even mentioning it in the spec for the most part
<balrog>
hah.
<gruetzkopf>
the first few diagrams do show it
<whitequark>
yes but it's not normative
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<whitequark>
there's one normative sentence I can see: that an USB4 hub shall include an USB 2 hub
<balrog>
doesn't USB 2 work over different pins?
<cr1901_modern>
So USB2 vs USB4 is like PCI vs PCIe? The device/config/interface/endpoint/inout stuff is still the same right?
<gruetzkopf>
i'm only on page 122
* cr1901_modern
is not reading it just yet
<azonenberg_work>
wait
<azonenberg_work>
usb 4 exists now?
<gruetzkopf>
yes
<azonenberg_work>
is it as cursed as the previous versions?
<gruetzkopf>
potentially more so
<azonenberg_work>
do you need a small x86 core to run the host contrller?
<azonenberg_work>
:p
<whitequark>
azonenberg_work: it's like an order of magnitude more complex
<azonenberg_work>
with two linux kernels in the hub chipset?
<gruetzkopf>
it supports 6 retimers between any port pair
<gruetzkopf>
you can talk to all of them
<whitequark>
with configurable equalization yes
<whitequark>
two on one side, two on another, two in the active cable
<whitequark>
azonenberg_work: it borrows heavily from PCIe, but it also makes PCIe look simple by comparison
<whitequark>
it has an incredibly complicated grandmaster clock hierarchy for example, including clock synchronization between multiple domains
<azonenberg_work>
wtf
<whitequark>
also, it can embed PCIe, of course
<azonenberg_work>
Of course
<azonenberg_work>
dma attacks up the wazoo?
<whitequark>
so you have half-of-PCIe layered on top of I-can't-believe-it's-not-PCIe
<gruetzkopf>
(you must also be able to embed DP)
<whitequark>
with weird restrictions like "you have to permute the ordered sets like this"
<whitequark>
azonenberg_work: PCIe ACS is required
<azonenberg_work>
ACS?
<whitequark>
access control system
<whitequark>
request tagging for IOMMU
<azonenberg_work>
wanna bet it wont be properly implemented?
<whitequark>
sucker bet
<whitequark>
the system shall provide some implementation-specific protection against rogue endpoints.
<whitequark>
great
<whitequark>
that's basically all it says on the topic, it's like one page
<whitequark>
azonenberg_work: USB4 topology includes explicit routers in every hub, and the HCI provides 8 labels for every packet
<whitequark>
and the router on level n looks at nth label
<whitequark>
oh by the way
<gruetzkopf>
ACS is pretty much fucked on all systems
<whitequark>
the way you add USB2 downstream ports in USB4 hubs is by hanging an USB2 HCI off the PCIe router inside the hub
<whitequark>
so you can't just not implement the PCIe part
<mwk>
you what
<whitequark>
yes really
<cr1901_modern>
this sounds like a disaster
<gruetzkopf>
this sounds like my kind of disaster
<whitequark>
I *think* they *also* add a mux so you can plug the hub into an USB2 host
<azonenberg_work>
on the plus side, if this is actually the case
<whitequark>
but I assume that if you plug it into an USB4 host, the mux switches to the internal HCI
<azonenberg_work>
you could have multiple usb2 interfaces off a single usb4 root
<azonenberg_work>
with >480 Mbps total throughput?
<gruetzkopf>
yes
<whitequark>
azonenberg_work: the reference diagrams in the spec show a single USB2 hub inside
<azonenberg_work>
that was a big problem for me on usb3, you could not have many usb2 devices sharing a 5 Gbps link
<whitequark>
so I assume that's how everyone will implementit
<azonenberg_work>
whitequark: ok so maybe you need a tree of hubs
<whitequark>
oh right
<whitequark>
of course they will
<azonenberg_work>
one root usb4 hub with two usb 2-4 downstream hubs
<whitequark>
because you have to be able to mux the hub to the UFP 2.0 pairs
<whitequark>
yeah
<whitequark>
that would work
<azonenberg_work>
wouldnt that give you two usb2 hci's and thus 2*480M bandwidth?
<whitequark>
but... I expect USB4 hubs would be extremely expensive
<azonenberg_work>
still it sounds like a trainwreck
<whitequark>
because each port has to give you USB3, USB4, DP, and if the hub is TBT3-compatible, TBT3
<whitequark>
the yields on that will be *horrible*
<whitequark>
hell, there aren't any >2 port TBT3 chipsets on market
<azonenberg_work>
meanwhile 40G ethernet does away with all of this nonsense and is just four bonded 10G 64/66b diffpairs
<whitequark>
USB4 is two bonded 20G links
<azonenberg_work>
50G ethernet is two bonded 25G 64/66b (i think) diffpairs
<whitequark>
or two bonded 10G links depending on the host (I think)
<azonenberg_work>
Yes but it's not running all this insane protocol stack and multiple links etc on top of it
<whitequark>
the power consumption of that is also going to suck
<azonenberg_work>
it's just 802.3 framing
<azonenberg_work>
any ethernet is just ethernet, all ethernet ports of a given speed are compatible
<whitequark>
yeah I know
<whitequark>
I've been pushing ethernet where I'm able to
<azonenberg_work>
not the disaster you have now, where for example
<whitequark>
Glasgow revE will encapsulate Ethernet over USB3
<whitequark>
and not support any other USB3 operation
<azonenberg_work>
my laptop i'm typing this on has two usb A ports
<azonenberg_work>
and two usb C ports
<azonenberg_work>
but one of the usb C ports is a power input (only, i think)
<azonenberg_work>
the other one, right next to it, is normal usb C and displayport
<azonenberg_work>
plugging into the wrong one blind is very easy and will result in whatever you plugged in not working
<azonenberg_work>
i.e. no charging or no video
<whitequark>
yes, macbooks already solve that
<whitequark>
4 USB C port macbooks support everything on every USB port
<whitequark>
it requires two TBT3 controllers
<whitequark>
and a shitton of DP muxing
<gruetzkopf>
i guess usb4 is trying to solve that
<whitequark>
I don't think they can upgrade it to 6 easily
<whitequark>
yes
<whitequark>
but... I want to see that silicon first
<whitequark>
I have serious trouble believing they can do it reliably and at any reasonable cost
<azonenberg_work>
I remain skeptical. Lol
<gruetzkopf>
i mean alpinerige has two dedicated DP puts and a MST capable DP output, plus pcie plus 2* TBT3
<azonenberg_work>
i will continue to push ethernet as the interconnect of choice for everything
<whitequark>
azonenberg_work: no argument from me
<azonenberg_work>
i'm actually truly impressed at how un-cursed the IEEE has managed to make ethernet
<azonenberg_work>
compared to almost every other protocol i've looked at from the PC industry
<davidc__>
azonenberg_work: probably because the people contributing to it actually have to make the silicon
<davidc__>
(and are not intel?)
<azonenberg_work>
The fact that you can seamlessly route packets from a v.92 modem attached over rs232 to a 100G router, given a few switches or media converters in the path
<azonenberg_work>
and have application layer just work across it
<whitequark>
yeah
<azonenberg_work>
using the exact same framing and protocol stack
<azonenberg_work>
just a different phy
<azonenberg_work>
Nothing else can do that, or even come close
<gruetzkopf>
During phase 1, Router A discovers the following connection information:
<gruetzkopf>
• Whether or not there is a reverse insertion at the USB Type-C® connector.
<gruetzkopf>
• Whether or not the Link is USB4.
<gruetzkopf>
• Whether or not it is connected by an Active Cable that contains Re-timers.
<gruetzkopf>
• If connected by an Active Cable that contains Re-timers, whether or not the cable is a TBT3 Active Cable (See Section 13.2.1.1).
<gruetzkopf>
• If not connected by an Active Cable that contains Re-timers, whether or not Cable supports Gen 3 speed.
<gruetzkopf>
aaaaaaaaaaa
<azonenberg_work>
meanwhile when i plug a SFP+ module into my switch, IDGAF if it's multimode, singlemode, baseT, passive direct attach, or buffered/retimed direct attach
<azonenberg_work>
I spit out 802.3 framing in 64/66b line code at 10.3125 Gbps and i get that out the other end
<azonenberg_work>
it doesnt matter what happens in between
<azonenberg_work>
the difference in needless complexity is staggering
<whitequark>
azonenberg_work: to be fair, you can't tunnel PCIe over that
<whitequark>
or DisplayPort for that matter
<gruetzkopf>
there's an ethertype for that
<davidc__>
I believe we call that a challenge
<azonenberg_work>
oh, and usb is just now pushing 40G in a proposed spec, while ethernet is working on... 400G now?
<azonenberg_work>
whitequark: re pcie over ethernet...
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<davidc__>
azonenberg_work: TBF, ethernet 25/40G/50G/100G is not something one would want in a home environment
<azonenberg_work>
davidc__: oh?
* azonenberg_work
looks towards pile of QSFP modules and cables awaiting installation
<whitequark>
sure does, that's what the thunderbolt external docks do, if you want to play games on a laptop
<azonenberg_work>
because last time i checked new manufacture SFP+ modules from fs.com were $39 per port and i suspect if you shopped secondhand on ebay etc, or aliexpress, you could get a fair bit less
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<gruetzkopf>
new SR SFP+ are like 14€ new on FS
<whitequark>
azonenberg_work: intel x520 costs $100 per adapter
<azonenberg_work>
it could be less?
<azonenberg_work>
But considering new 1G SFPs are like $6 on FS
<azonenberg_work>
and i've got used ones for 80 cents on ebay
<azonenberg_work>
i expect 10G can be had for a similar discount
<gruetzkopf>
i have a literal bucket of SFPs
<azonenberg_work>
i have more 1G SFPs than i know what to do with
<azonenberg_work>
i think i got 25 for $20 once
<azonenberg_work>
then did it again a few weeks later
<azonenberg_work>
then as far as switch ports go, i got a nexus 3064 which is 48x 10g SFP and 4x 40G QSFP+ splittable to 16x more 10g
<azonenberg_work>
for... something under $500 on ebay iirc
<azonenberg_work>
So $7-8 per switch port
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<azonenberg_work>
then $18 per sfp new, i see $7.97 per sfp on ebay
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<gruetzkopf>
40G nics can be had used for like 50€/port
<azonenberg_work>
NICs are indeed the expensive part, i see an x520-da2 on ebay for $65 ($32 per port)
<azonenberg_work>
an off-brand one for $55
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<whitequark>
so i need two and then a thunderbolt thing for my laptop
<azonenberg_work>
then a mellanox pcie single port 10g nic for $27.95
<azonenberg_work>
an hp dual port one for $22
<azonenberg_work>
a solarflare dual port for $39
<whitequark>
mhm
<whitequark>
ok that starts being not so bad
<azonenberg_work>
So yeah it's not excessive - not as cheap as 1G but not beyond reason
<azonenberg_work>
then as far as adding it to an FPGA board, you need an FPGA with 10G transceivers, or an FPGA with four 3G transceivers and a $20ish converter chip (which does two lanes, single lane is likely cheaper), and a $3ish connector
<azonenberg_work>
40G starts getting pricey, the only reason i have a single 40G nic is because of a customer buying it for me
<azonenberg_work>
and an fpga board with them on it
<azonenberg_work>
(actually the fpga ports are 100G but the optics are only 40G)
<azonenberg_work>
i only have 10G deployed right now, the 40G interfaces arent wired up yet
<gruetzkopf>
my 40GE card is mellanox, but i'm using it at 10G currently
<davidc__>
azonenberg_work: "home environment" in terms of heat output/power dissipation, and hence the fans required to cool it
<GenTooMan>
let me jokingly say "early adopters sheesh"
<davidc__>
I've used a bunch of 100G stuff through work; but even at idle without links up that gear was loud
<davidc__>
With more than a few 100G links up it was best approached with ear protection
<azonenberg_work>
davidc__: lol
<azonenberg_work>
You saw my tweet about my 10/40G cisco right?
<GenTooMan>
davidc__ those aren't water cooled? that would allow them to increase surface area and have less of a tornado.
<davidc__>
GenTooMan: When you have $xmil of equipment in a rack, you don't want something full of water at the top of it
<GenTooMan>
davidc__ I suppose you could liquid cool it with hydrocarbons (IE watch it boil in a hydro carbon bath) no easy solutions I guess. Also the issue with water cooling is what happens when hoses break. What is the typical life span 10 years or 5 years for your equipment? I'm use to 40 years so materials I saw in use are insanely expensive and difficult to work with.
<whitequark>
you can use galden to cool it
<whitequark>
perfluorocarbons
<whitequark>
except that costs 500 EUR per kilo on its own
<davidc__>
I mean, these are all things you could do; but these devices go into datacenters. Datacenters that are built to provide cold air entering one side of the device, and to remove hot air exhausting from the others
<whitequark>
that too
<implr>
iirc ovh does watercooling with some centralized rack system
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<GenTooMan>
Well if you go acording to the laws of thermodynamics you will eventually hit a brick wall with air cooling and compact electronics. You can use more efficient processes such as gallium nitride that helps immensely but nothing is free. Silicon carbide is really great but ... expensive and difficult to work with. No easy solution really.
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<balrog>
whitequark: so is there enough info in the spec to implement thunderbolt 3 backwards compatibility?
<whitequark>
balrog: absolutely none
<whitequark>
they bolted TBT3 on the side
<balrog>
then how are you supposed to make a compliant USB4 device
<whitequark>
it's not required
<whitequark>
USB4 adds yet another PCIe encapsulation
<balrog>
oh, fun.
<balrog>
so TBT3 will remain closed forever
<whitequark>
likely
<whitequark>
it even uses a different PHY
<whitequark>
(afaict)
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<gruetzkopf>
at least a different set of link speeds
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<guan>
has anyone here tried the linux/litex/vexriscv stuff on the versa board?
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