freeemint has quit [Remote host closed the connection]
freeemint has joined ##openfpga
freeemint has quit [Read error: Connection reset by peer]
freemint has joined ##openfpga
Bike has quit [Ping timeout: 272 seconds]
freemint has quit [Ping timeout: 245 seconds]
Bike has joined ##openfpga
freemint has joined ##openfpga
freemint has quit [Remote host closed the connection]
freemint has joined ##openfpga
freemint has quit [Ping timeout: 264 seconds]
rohitksingh has joined ##openfpga
freemint has joined ##openfpga
Bike has quit [Quit: Lost terminal]
pie_ has quit [Quit: pie_]
Jybz has joined ##openfpga
rohitksingh has quit [Ping timeout: 276 seconds]
emeb_mac has quit [Ping timeout: 246 seconds]
freemint has quit [Ping timeout: 250 seconds]
Maya-sama is now known as hackkitten
Asu has joined ##openfpga
edmund has quit [Quit: Ex-Chat]
Bob_Dole has quit [Ping timeout: 276 seconds]
AndrevS has joined ##openfpga
Asu has quit [*.net *.split]
X-Scale has quit [*.net *.split]
uovo has quit [*.net *.split]
dkozel has quit [*.net *.split]
yhetti has quit [*.net *.split]
oeuf has quit [*.net *.split]
implr has quit [*.net *.split]
horizon has quit [*.net *.split]
Lord_Nightmare has quit [*.net *.split]
duck2 has quit [*.net *.split]
bsilvereagle has quit [*.net *.split]
kristianpaul has quit [*.net *.split]
ZirconiumX has quit [*.net *.split]
pepijndevos has quit [*.net *.split]
mifune has quit [*.net *.split]
balrog has quit [*.net *.split]
davidc__ has quit [*.net *.split]
craigjb has quit [*.net *.split]
Prf_Jakob has quit [*.net *.split]
rvense has quit [*.net *.split]
marcan has quit [*.net *.split]
Ekho has quit [*.net *.split]
cblam has quit [*.net *.split]
keesj has quit [*.net *.split]
anuejn has quit [*.net *.split]
mossmann has quit [*.net *.split]
tnt has quit [*.net *.split]
felix_ has quit [*.net *.split]
Sprite_tm has quit [*.net *.split]
goran-mahovlic_ has quit [*.net *.split]
zignig has quit [*.net *.split]
yhetti has joined ##openfpga
mifune has joined ##openfpga
ZirconiumX has joined ##openfpga
uovo has joined ##openfpga
oeuf has joined ##openfpga
duck2 has joined ##openfpga
bsilvereagle has joined ##openfpga
dkozel has joined ##openfpga
felix_ has joined ##openfpga
mifune has quit [Changing host]
mifune has joined ##openfpga
X-Scale has joined ##openfpga
bsilvereagle has quit [Changing host]
bsilvereagle has joined ##openfpga
kristianpaul has joined ##openfpga
horizon_ has joined ##openfpga
zignig has joined ##openfpga
anuejn has joined ##openfpga
Asu has joined ##openfpga
cblam has joined ##openfpga
balrog has joined ##openfpga
Lord_Nightmare has joined ##openfpga
craigjb has joined ##openfpga
implr has joined ##openfpga
keesj has joined ##openfpga
Sprite_tm has joined ##openfpga
rvense has joined ##openfpga
tnt has joined ##openfpga
mossmann has joined ##openfpga
davidc__ has joined ##openfpga
marcan has joined ##openfpga
Prf_Jakob has joined ##openfpga
goran-mahovlic has joined ##openfpga
pepijndevos has joined ##openfpga
dkozel has quit [Changing host]
dkozel has joined ##openfpga
Ekho has joined ##openfpga
freemint has joined ##openfpga
freemint has quit [Ping timeout: 250 seconds]
freemint has joined ##openfpga
freemint has quit [Ping timeout: 268 seconds]
Bob_Dole has joined ##openfpga
freemint has joined ##openfpga
kristianpaul has quit [Quit: WeeChat 1.9.1]
kristianpaul has joined ##openfpga
emeb has joined ##openfpga
<ZirconiumX>
Have I mentioned that Quartus is misery? Because Quartus is misery.
<mwk>
who would have expected
<mwk>
found any funny bugs yet?
<ZirconiumX>
I managed to get it to ICE at one point
<mwk>
that's... honestly I'm not even surprised
<ZirconiumX>
So I'm trying to build a MiSTer core for the C64
<ZirconiumX>
PnR took 10m16s and it's still not finished building
<ZirconiumX>
14m42s for this
<ZirconiumX>
Uuuugh
<mwk>
umm
<mwk>
you... consider this long?
<ZirconiumX>
I'm used to software, not hardware :P
<whitequark>
mwk: i consider anything over 30s long
<mwk>
I mean, you're right of course, but
<whitequark>
lol
<whitequark>
my standards are set by nextpnr
<mwk>
you know
<whitequark>
i know.
<ZirconiumX>
Apparently people have begged Intel to produce a crappy PnR algorithm to cut down on synthesis time
<ZirconiumX>
Anyway, main reason I've done this is to inspect the resulting netlist
* mwk
's student had lots of "fun" with his homework for my course, 6h build time
<mwk>
in the end we didn't test the version after all fixes, the cycle time was just fucking impossible, I just looked at it and said "ok, no more bugs I can find"
<ZirconiumX>
Okay, who wants to bet how long it takes Yosys to parse the resulting netlist?
<ZirconiumX>
687,143 lines of Verilog RTL
<mwk>
simple raytracer for virtex 5 + ISE
<whitequark>
ZirconiumX: parse? under 3 minutes let's say
<tnt>
I have ice40 builds that take 5-10 min ...
<ZirconiumX>
Parsing was fast, but the RTLIL takes a little longer
<whitequark>
tnt: i don't have that much patience
<ZirconiumX>
^
<whitequark>
so if a design is that slow, i fix the design to be less slow
<whitequark>
or change the problem to not require such a slow design
<tnt>
Heh, I routinely do 3h Kintex7 builds for work :p
<whitequark>
no, if i'm paid by the hour that's a different story
<whitequark>
i'll make myself some tea and...
<ZirconiumX>
That's a good call, actually; time for some tea
<tnt>
Surprisingly in that design the placer is not all that slow, it's the _routing_ step of next pnr that takes forevever.
<ZirconiumX>
whitequark: By now I think you've lost the bet
<emily>
I'm kind of glad I didn't try doing FPGA stuff before the FOSS toolchain
<emily>
so I don't have the messed up low standards the vendor toolchains give people
<whitequark>
ZirconiumX: shit
<whitequark>
although, i did specifically say "parse"
<whitequark>
so if it's out of read_verilog...
<tnt>
emily: The UI and 'experience' of vendor toolchains is not ideal. But my experience is the generated logic/bistream is pretty good.
<ZirconiumX>
It is read_verilog, yeah
<ZirconiumX>
Still going...
<ZirconiumX>
At this point `grep` would be fastetr
<ZirconiumX>
-t
<whitequark>
tnt: the problem here is that generations of HDL developers raised on these awful tools are stuck into thinking that this is in any way acceptable
<whitequark>
i refuse to contribute to that in any way if i can avoid it at all
<ZirconiumX>
As far as I can tell from the Quartus documentation, ALMs can produce both normal and inverted signals
<ZirconiumX>
So it'll happily spam inverters because they're "free"
<whitequark>
ah
<daveshah>
There's a rumour that the inverters are in the routing fabric
<daveshah>
(i.e. pips are inverting as inverting buffers are cheaper in CMOS)
<ZirconiumX>
daveshah: I'll let you know in three years time :P
<daveshah>
so an even number of buffers is non-inverted, odd is inverted
<daveshah>
UltraScale+ has something like this in its clock routing, but with programmable inversion at the final leaf level to compensate
<tnt>
emily: imho, it's not settled. They do tend to have a large "startup time" for sure and that's them being lazy for sure. And for something like the ice40 that's a high cost to pay which is why yosys-nextpnr appears much faster especially on a small designs. But on like a 90% full fpga where you try to get the last bit of timing you can, the startup time doesn't matter all that much.
<whitequark>
let's rephrase. glasgow is impossible with vendor tool performance
<whitequark>
there's an entire new area of designs relying on fast (partial, where it exists) reconfiguration that just doesn't exist because the toolchains are too slow and cumbersome
<whitequark>
good job crippling one of the things FPGAs are inherently excellent at
<daveshah>
Hehe I might actually have a demo of that in an hour or two (trying the SEI partial thing for ECP5 that you found)
<whitequark>
:D :D
<whitequark>
i wonder if this might even allow me to get rid of the FX3 in revE?
<whitequark>
unlikely, but
<gruetzkopf>
that would be fun
genii has joined ##openfpga
<ZirconiumX>
By the way, Yosys PR #1318 makes me sad
<ZirconiumX>
Because `altsyncram` is a megafunction and fundamentally the wrong thing to use here
<ZirconiumX>
Unfortunately, what the *right* thing to use here is confusing
Jybz has quit [Quit: Konversation terminated!]
Jybz has joined ##openfpga
Jybz has quit [Ping timeout: 252 seconds]
Jybz has joined ##openfpga
Bob_Dole has quit [Read error: Connection reset by peer]
s_frit has quit [Remote host closed the connection]
s_frit has joined ##openfpga
<tnt>
So just to provide some numbers: on audio-yamaha-opl yosys+nextpnr(HeAP) 6s, yosys+nextpnr(SA) 13s, icecube2 (simplify) 25s, icecube2 (LSE) 70s (wtf LSE itself is actually much faster but the placers chokes on the output ?!?)
<whitequark>
synplify?
<whitequark>
yeah
<whitequark>
HeAP is almost 5 times faster lol
<tnt>
Yeah. I wanted to also try on a more complex applet (that use more than 5% of the fpga) but not sure there is any ...
<whitequark>
none that build out of the box i think
<whitequark>
the vga terminal one is more complex but it's broken
<tnt>
ICESTORM_LC: 9185/ 5280 173%
<tnt>
yeah :)
flyback has quit [Ping timeout: 276 seconds]
<implr>
don't some vendor tools (vivado specifically) spend an absurd amount of time in flexlm licensing/decryption code as well?
<whitequark>
well i tried running vivado with flexlm and without flexlm and didn't notice any difference
<whitequark>
but maybe it's different if you use their "intellectual poverty" cores
<implr>
i recall reading somewhere on birbsite that a lot of function calls are indirect for no reason other than allowing decryption or something
<daveshah>
I think you also need flexlm for the larger non free devices
<implr>
but i might be misremembering
<Hoernchen>
the amazing size of the binaries is at least on windows 90% obfuscation
<whitequark>
well they sure forgot to obfuscate the flexlm parts
<whitequark>
i'm not sure about others but ...
<whitequark>
ah yeah, on linux, not sure about windows
<gruetzkopf>
okay,, how do i, for litedram, even find out the IO names i need to constrain
<gruetzkopf>
use: S6LX150, 32Mx16 memory, ISE
<gruetzkopf>
lets read s6ddrphy.py
freeemint has joined ##openfpga
freemint has quit [Ping timeout: 245 seconds]
freeemint has quit [Ping timeout: 264 seconds]
rohitksingh has joined ##openfpga
<azonenberg>
whitequark: i was told a while ago by someone in this channel that some of the secureip code on linux, at least, is a giant pile of rop gadgets
<azonenberg>
they literally make a massive rop chain then ret into it to do the secureip processing
<azonenberg>
which i'm sure plays *hell* with branch prediction etc
<ZirconiumX>
It's like procedurally generated abstract art
<ZirconiumX>
Unfortunately my mental IC placement algorithm isn't *quite* as refined
<emily>
spinny~
<emily>
it looks like it'll make me go dizzy and get hypnotised if I keep staring
<emily>
or maybe like one of those magic eye pictures that I could never get to work
<azonenberg>
ZirconiumX: playing with topr?
<ZirconiumX>
azonenberg: Indeed
<ZirconiumX>
Wondering how much I can "safely" scramble the bus headers to get them to play nicely with the routing
<Ultrasauce>
i love topr's routing so much
<ZirconiumX>
Unfortunately due to bugs in the KiCad script, this board won't make it to the fab
<ZirconiumX>
But it's fun to play with anyway
<ZirconiumX>
(top-level module parameters don't appear in the KiCad netlist for some reason)
<ZirconiumX>
(this means that Boneless has only input buses instead of output buses
<ZirconiumX>
)
<whitequark>
oh no
<ZirconiumX>
o_mem_data and o_ext_data are completely missing
<ZirconiumX>
However looking at the generated netlist gives me an idea for tristate shenanigans instead of muxes
<whitequark>
yea!
<ZirconiumX>
For example the very first thing it does is multiplex between the ext and mem buses
dh73 has joined ##openfpga
<emily>
nmigen can't do tristate stuff though, right?
<whitequark>
nop
<ZirconiumX>
It's a little confusing to read the netlist because of some names being lost in translation
<ZirconiumX>
For example, arb.$1_12
<whitequark>
emily: i mean, you could make an instance
<whitequark>
but ZirconiumX probably wants a techmap rule for muxes
<ZirconiumX>
whitequark: I think to get any more performance out of this I would need to write a C++ pass to manipulate RTLIL
<ZirconiumX>
I've attempted to keep it as a script pass, but there are things I can't do
<whitequark>
yea
<ZirconiumX>
Outside of modifying the RTL
<ZirconiumX>
Additionally, I think TopoR would benefit greatly from knowing it can swap gates
<ZirconiumX>
It seems like it can, but it's undocumented
<ZirconiumX>
Or perhaps untranslated
Bike has joined ##openfpga
horizon_ is now known as horizon
horizon has quit [Changing host]
horizon has joined ##openfpga
emeb_mac has joined ##openfpga
<mwk>
azonenberg: "securep code"?
<mwk>
sn't that just that verlog wth aes?
<ZirconiumX>
mwk: having issues with your I key?
<mwk>
ZirconiumX: yeah
<mwk>
my laptop eyboard s broen and can't be bothered to st up and search for the USB one
<mwk>
(whole column of eys between 7ujm and 9ol.)
<whitequark>
lol
emeb_mac has quit [Read error: Connection timed out]
emeb_mac has joined ##openfpga
<emily>
don't die
marcan has quit [Ping timeout: 264 seconds]
marcan has joined ##openfpga
Asu` has joined ##openfpga
Asu has quit [Ping timeout: 258 seconds]
AndrevS has quit [Remote host closed the connection]
<GenTooMan>
whitequark are their any "new" migen examples?
<whitequark>
i'm not sure i understand the question
<ZirconiumX>
TFW when the closest thing to a corporate tutorial video is a small channel called MrsMaple81
Jybz has quit [Ping timeout: 246 seconds]
<azonenberg>
mwk: i mean the code that decrypts it
<azonenberg>
it's... not straightforward aes
<azonenberg>
they are, i think, trying to protect the private key
<ZirconiumX>
whitequark: So I've conducted some experiments using the Yosys (CMOS?) `synth` script, and it seems to be making a complete mess of your ALSRU
<whitequark>
unsurprising
Zorix has quit [Quit: Leaving]
<whitequark>
it was written for LUT architectures with ripple carry
<whitequark>
that's why it's pluggable
<ZirconiumX>
Adder inference works here at least
<ZirconiumX>
But mux inference gets completely screwed
<ZirconiumX>
I could probably just reimplement your model and it'd be better than what Yosys could do
<whitequark>
quite possibly
<whitequark>
i mean
<whitequark>
if i was doing boneless in hard logic i'd like
<whitequark>
design it from scratch in HDL but instantiate that hard logic
<whitequark>
and prove equivalence
<ZirconiumX>
I'd probably make it a bit more parallel prefix though
<whitequark>
parallel prefix?
Zorix has joined ##openfpga
<ZirconiumX>
It's the term I've known it under; Wikipedia calls it "prefix sum"
<whitequark>
i'm not familiar with applications of this
<ZirconiumX>
The Kogge-Stone adder uses it to great effect