<GenTooMan>
whitequark Sorry about I got lost with nmigen, well nmigen isn't different enough from verilog it takes some rethinking. The misoc example is 4 years old and not nmigen clearly.
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<_whitenotifier>
[libfx2] whitequark created branch travis-synth - https://git.io/fjAQS
<_whitenotifier>
[whitequark/libfx2] whitequark created branch travis-synth https://git.io/fjAQ9
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<gruetzkopf>
may be able to poke at the panologic g2 again this night (after i restore object permanence data on my glasgow..)
<whitequark>
object what
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<ZirconiumX>
whitequark: So, Boneless is meant to be 4 CPI, right? Read reg1, read reg2, op, write.
<whitequark>
yeah
<ZirconiumX>
But don't you also need to do an instruction fetch?
<whitequark>
sorry
<whitequark>
fetch/decode, read1, read2, write
<whitequark>
and the ALU is combinatorial
<ZirconiumX>
Ah, I see, that's where I misunderstood
<ZirconiumX>
Thank you
<whitequark>
not saying it's a good design fwiw
<whitequark>
maybe I should target more like 6 cpi
<sorear>
does boneless have a picorv32-like explicit goal of “high fmax even at the expense of perf so that users don’t need another clock domain”?
<whitequark>
sorear: yes
<whitequark>
48M on iCE40HX
<ZirconiumX>
I managed to save a chip by reworking the design a little, I'm proud of myself#
<ZirconiumX>
-#
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<ZirconiumX>
So, for those who don't know, Boneless' ALU takes in a shift-right bit, plus a 3-bit operation code
<ZirconiumX>
In my design the ALU is essentially 74153 MUX4s feeding into a 74283 adder
<ZirconiumX>
So it looks like F_a(A, B) + F_b(a, B) for arbitrary F_a and F_b
<ZirconiumX>
(essentially they're LUT2s)
<ZirconiumX>
But for essentially any non-arithmetic operation, F_b is always-zero
<ZirconiumX>
The 74153 has a per-multiplexer output-enable which returns low if the pin is low
<ZirconiumX>
So I can make the non-arithmetic operations a don't-care state and wire up the output enable to go low on any non-arithmetic operation
<whitequark>
cute
<ZirconiumX>
Essentially it trades 2/3 AND gates (I have a single AND gate spare) for a single AND and an inverter
<ZirconiumX>
Actually just an inverter, because NOT (NOT A AND NOT B) == A AND B
<sorear>
A OR B. De Morgan
<ZirconiumX>
...You're right, I misread the symbol
<ZirconiumX>
(seriously, why did the mathematicians have to use ^ and v?)
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<ZirconiumX>
So I've been sketching out the timing for Boneless. So far the ALU alone accounts for 110ns of worst-case propagation delay, and it's not even complete
<whitequark>
yeah like I said Boneless isn't super great ;w;
<ZirconiumX>
Sure, but I suspect an unnecessary dependency chain in my logic
<ZirconiumX>
It'd be grand if the Liberty cell format didn't choose an unnecessarily complicated way to explain timing
<ZirconiumX>
Human readable timing: (min, typical, max)
<ZirconiumX>
The description of the machine readable timing field is itself only machine readable