<ZirconiumX>
Sadly at 35cmx35cm it won't be cheap :P
<Flea86>
Really need an autoroute button...
<ZirconiumX>
This is TopoR
<ZirconiumX>
It's an autorouter :P
<Flea86>
I've not heard of it! Interesting.
<ZirconiumX>
WQ recommended it
<ZirconiumX>
It's pretty great, when it doesn't hang, or reject your .dsn
<whitequark>
lol
<Flea86>
lol
<whitequark>
I've used it like once
<whitequark>
it's more that
<whitequark>
this is about the only autorouter with autoplacer I know
<whitequark>
and one of few that can do a board that's this much of a ratsnest
<Flea86>
If that's routed, I'd want my money back :P
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<whitequark>
what's the problem?
<Flea86>
whitequark: I was expecting a nicely routed board, not a ratsnest
<Flea86>
Seriously though, doesn't matter to me I do my own routing.
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<whitequark>
Flea86: it *is* nicely routed
<whitequark>
that's the whole thing about TopoR
<whitequark>
it routes topologically, that is, uses shortest path given DRC
<whitequark>
it is specifically designed to *not* route like a human in the 80s
<whitequark>
they claim it gives better results ("the only autorouter capable of 1L boards"), which i have found is true, and better EMC, which is plausible but I haven't verified it
<ZirconiumX>
Something I find is that in the postprocessing pass where it draws arcs between points is that it generally introduces DRC violations on an otherwise violation-free design, whitequark
<whitequark>
hmm
<Flea86>
whitequark: Fair enough. I do get the benefits of direct point-to-point wiring. To be fair, I've actually used an autorouter commercially (and it doesn't look a great deal better asthetically). It worked, but I refrained from showing my boss the work :)
<ZirconiumX>
Aesthetics are fairly meaningless
<ZirconiumX>
In this case at least
<whitequark>
indeed
<ZirconiumX>
You know you've got a good design when running DRC incapacitates KiCad for 10 minutes (not exaggerating)
<pie_>
("Routing Concepts of a Topological Router CAD System" does not seem to be accessible anywhere >.>)
<pie_>
(of course it fails on the site of the TopoR people)
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<sensille>
wayback machine?
<pie_>
checked it :I
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<ZirconiumX>
The copper pours look rather weird with a TopoR board
<ZirconiumX>
The whole thing looks very unnatural
<ZirconiumX>
Which means Boneless probably qualifies as a work of art no
<ZirconiumX>
I rendered tpw_rules' update to the Boneless manual, and it's very nice to read, honestly
<ZirconiumX>
whitequark: Is EXTI followed by an instruction which doesn't care about it defined or not?
<whitequark>
ZirconiumX: undefined
<tpw_rules>
thank you ZirconiumX. the latest render should be in the PR too though
<tpw_rules>
i effectively turned that situation with EXTI into a nop
<ZirconiumX>
I'm curious if I can beat the compiler, since despite our best efforts (okay they maybe we're our *best*, but) Yosys doesn't recognise constructs like counters
<whitequark>
mhm
<whitequark>
there should only really be one counter, pc
<whitequark>
ok two
<ZirconiumX>
I mean, W comes to mind
<whitequark>
ah yeah
<whitequark>
sure
<ZirconiumX>
I'll have to read the wording, but it sounds like anything which touches W requires a full register spill/restore?
<tpw_rules>
no, the registers are in main memory at all times
<ZirconiumX>
That's going to complicate things then
<tpw_rules>
logically
<tpw_rules>
i mean you could keep them in a register file as long as you read the register file whenever memory in W to W+8 was accessed
<ZirconiumX>
So if you do ADD R0, R1, R2; you have to load R1 and R2, add, then store?
<whitequark>
ZirconiumX: that *simplifies* things
<whitequark>
well
<whitequark>
in a way
<whitequark>
it's a bit like 8051
<whitequark>
and yes
<ZirconiumX>
[15:03:18] tpw_rules: i mean you could keep them in a register file as long as you read the register file whenever memory in W to W+8 was accessed <--- I'd have to implement a method to only spill modified registers, then.
<tpw_rules>
i mean you don't neeeeed to
<ZirconiumX>
Memory is a painful thing for 7400 logic, because finding DIP RAM is almost impossible nowadays
<whitequark>
tpw_rules: but you'd still have to write through to RAM
<whitequark>
at which point you're better off making a normal cache
<whitequark>
without being W-specific
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<ZirconiumX>
whitequark / tpw_rules: I was talking to a friend about the ISA manual. There's a slight inconsistency between the overflow flag being V, but jump on overflow being JO.
<ZirconiumX>
For example, JS/JC are named after the flags they check
<whitequark>
ZirconiumX: oh
<whitequark>
good point
<whitequark>
I used to have JV as "Jump Virtual"
<whitequark>
but it's now "Jump Virtual Table"
<whitequark>
so JVT
<whitequark>
so we can jave JV and JNV
<whitequark>
tpw_rules: feel free to rename!
<ZirconiumX>
Also the names LDW/STW are maybe a bit confusingly named, too?
<ZirconiumX>
Since they're more about saving/restoring W
<whitequark>
mmm, yes, but I didn't come up with better names
<ZirconiumX>
SAVEW/RSTRW?
<whitequark>
needs to be 4 letters
<ZirconiumX>
SVW, RSW?
<whitequark>
it's not just save/restore
<whitequark>
it also moves the pointer
<tpw_rules>
pshw/popw?
<tpw_rules>
i'll look at it tonight. i'm trying to do dc motor control systems at the moment
<whitequark>
it doesn't do that
<tpw_rules>
it kind of does, if you imagine the register window as a stack
<whitequark>
yes but "push w" sounds like you'd push the w register
<ZirconiumX>
Well, ADJW would be push, no?
<whitequark>
maybe GETW/SETW
<ZirconiumX>
That sounds better
<ZirconiumX>
whitequark: Also, what about saving/restoring flags?
<whitequark>
ZirconiumX: not currently possible
<ZirconiumX>
It seems like Boneless doesn't support interrupts, so there's at least that
<whitequark>
yeah
<whitequark>
both of these need to be fixed, really.
<ZirconiumX>
Without interrupts, flags are atomic
<whitequark>
but first i need an implementation that's less awful.
<whitequark>
i really don't like how slow the current one is.
<ZirconiumX>
Is that because of the memory ops?
<whitequark>
i'm not totally sure
<ZirconiumX>
It'd be nice if there was a way of getting the longest combinational path
<ZirconiumX>
In Yosys or something
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<whitequark>
yes, I was thinking about this pass
<whitequark>
I'll write it one day I guess
<ZirconiumX>
There's ltp, which is not necessarily combinational
<daveshah>
in the case of unit delays `ltp` with selection syntax to remove FFs should work
<whitequark>
oh nice
<whitequark>
`ltp -noff` ?
<daveshah>
That disables built in FFs
<whitequark>
ah
<daveshah>
for a non-generic-techonology-mapped design you'll need to use selections for the same effect
<ZirconiumX>
225 ALMs for the core FSM on Cyclone V, whitequark
<ZirconiumX>
~90MHz
<whitequark>
is that good or bad
<ZirconiumX>
I'll build some other things to give you comparison points
<ZirconiumX>
80MHz for core-fsm+memory
<whitequark>
hm
<ZirconiumX>
For lack of an alternative: PicoSoC is 5,955 ALMs at ~93MHz
<ZirconiumX>
whitequark: ^
<ZirconiumX>
If you have other comparison points you want testing, do tell
<whitequark>
hm
<whitequark>
i need to make it faster.
<ZirconiumX>
Maybe it's a design not well suited to iCE40?
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