<emeb>
I bet the yields on that die are just grrrrrreat!
<mwk>
it's 4 dies and superglue
<emily>
"and 1.5 Terabits of DDR4 memory bandwidth, which the company states will help its customers create designs featuring multiple VU19P chips in one system with all-to-all connectivity topology."
<implr>
for when you want to simulate a 256 core ryzen
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<hackerfoo>
I want to build a torus out of them.
<hackerfoo>
(VU19P FPGAs)
<hackerfoo>
What would you do if you had a million dollars? I'll tell you what I'd do, man: two VU19Ps at the same time, man.
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<emily>
lol
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<azonenberg_work>
hackerfoo: 2 fpgas 1 hackerfoo?
<azonenberg_work>
emeb: actually i bet yields are pretty decent
<azonenberg_work>
its made from four sub-dies that are each not too crazy
<azonenberg_work>
and presumably independently tested
<azonenberg_work>
all you have to worry about is packaging defects
<ZirconiumX>
Something something the magic of chiplets
<azonenberg_work>
Yep
<ZirconiumX>
I'm presuming the PnR algorithms are going to need to be aware of that, though
<daveshah>
Yes, there will be a reasonable timing cost to crossing SLRs
<azonenberg_work>
Yeah its not cheap, it's like a mini pad driver
<daveshah>
There are dedicated pipeline registers in the crossing, I think the tools will try to use registers as partition split points (most big designs will/should have lots of highly pipelined buses)
<azonenberg_work>
Yeah
<daveshah>
I have seen some people who just partition stuff manually
<azonenberg_work>
between cores, noc nodes, or whatever
<azonenberg_work>
On my vu9p's i just divided the system manually and floorplanned it, the design had obvious hierarchical boundaries in it i could split on
<daveshah>
Once I've got round to a router rewrite, I want to have a go at nextpnr for VU9P with RapidWright and EC2 F1
<azonenberg_work>
Nice
<azonenberg_work>
i havent had time to do much tooling work but i;'m slowly spinning up the ethernet switch project
<azonenberg_work>
i'm planning to try using a vcu118 for testing the switch fabric
<azonenberg_work>
with up to 8x 10G ports + 1x 1G it should have enough interfaces to stress it a bit
<daveshah>
Mmm, makes my zcu104 look like a whimpy piece of crap
<azonenberg_work>
Glad i didnt have to buy it myself. Lol
<azonenberg_work>
I didnt even buy my AC701, got a professor to fund that
<daveshah>
Hehe, I got an AC701 funded at uni and managed to blow it up on day 3 of using it (12V to 2.8V (latter derived from 3.3V and LDO failed short) fault on a FMC card)
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<azonenberg_work>
lol fun
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<gruetzkopf>
wow
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