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<tnt> Does anyone know what the "continuous read mode" in the picosoc spi controller is ?
<mwk> huh, wondered about that as well
<mwk> all I know is it hangs on my board
<tnt> Here I can enable it and it improves things a tiny bit. But I can't disable it.
<tnt> (it crashes)
* mwk investigates
<tnt> Oh, so apparently if you set some bit to 1 during one read command, for the next command you send, you don't have to sent the opcode, it assumes it will be the same command.
<mwk> huh
<mwk> you mean, this works with actually disabling CS#?
<mwk> that's... strange and kind of horrible
<tnt> mwk: yes. It just makes the next opcode implicit.
<tnt> (which is probably why disabling it crashes ...
<mwk> how is that even supposed to work
<mwk> you send just the address? how are you supposed to get out of this mode?
<tnt> well after the address you always have the 'dummy byte' which contains the mode bits which need to be set to a special value for this mode to stay enabled.
<mwk> ohh
<tnt> so you only enable it for the very next command.
<mwk> still horrible
<mwk> also explains why it doesn't work here, my SPI chip is shit
<tnt> it's a gain especially when you are in something like quad DDR mode where you can basically transfer 8 bits per clock cycle ... but the command is still in normal spi mode so you waste 8 cycles to transmit the command and then address + dummy + data is only 4 cycles.
<mwk> is there some sane way to reset it without upsetting the device if it's not currently in crazy mode?
<tnt> Sure, if you do a read ID command for instance. If it was in this mode, this will do a read at some random address and return garbage (but exit this mode) and if you were not in this mode, it will return the unique ID.
<mwk> I suppose that could be stuffed in the controller's state machine when starting up
<tnt> Looks like the flash I picked for my custom board doesn't support that mode though :/ Damn. The 16mbits version of the flash does support it, so that might be worth upgrading to that.
<mwk> hmm
<mwk> the controller does seem to attempt such a reset already, though
<mwk> it always sends a dummy 0xff command and then a dummy 0xab command on startup
<tnt> Oh I mean disabling it at runtime, not on reset.
<mwk> yes
<mwk> but changing the config register should restart the controller state machine
<mwk> softreset <= !config_en || cfgreg_we;
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