19:22 <tnt> Does anyone know what the "continuous read mode" in the picosoc spi controller is ?

19:27 <mwk> huh, wondered about that as well

19:27 <mwk> all I know is it hangs on my board

19:31 <tnt> Here I can enable it and it improves things a tiny bit. But I can't disable it.

19:31 <tnt> (it crashes)

19:36 <tnt> Oh, so apparently if you set some bit to 1 during one read command, for the next command you send, you don't have to sent the opcode, it assumes it will be the same command.

19:37 <mwk> huh

19:37 <mwk> you mean, this works with actually disabling CS#?

19:37 <mwk> that's... strange and kind of horrible

19:37 <tnt> mwk: yes. It just makes the next opcode implicit.

19:38 <tnt> (which is probably why disabling it crashes ...

19:38 <mwk> how is that even supposed to work

19:39 <mwk> you send just the address? how are you supposed to get out of this mode?

19:39 <tnt> well after the address you always have the 'dummy byte' which contains the mode bits which need to be set to a special value for this mode to stay enabled.

19:39 <mwk> ohh

19:39 <tnt> so you only enable it for the very next command.

19:40 <mwk> still horrible

19:40 <mwk> also explains why it doesn't work here, my SPI chip is shit

19:41 <tnt> it's a gain especially when you are in something like quad DDR mode where you can basically transfer 8 bits per clock cycle ... but the command is still in normal spi mode so you waste 8 cycles to transmit the command and then address + dummy + data is only 4 cycles.

19:43 <mwk> is there some sane way to reset it without upsetting the device if it's not currently in crazy mode?

19:46 <tnt> Sure, if you do a read ID command for instance. If it was in this mode, this will do a read at some random address and return garbage (but exit this mode) and if you were not in this mode, it will return the unique ID.

19:47 <mwk> I suppose that could be stuffed in the controller's state machine when starting up

19:53 <tnt> Looks like the flash I picked for my custom board doesn't support that mode though :/ Damn. The 16mbits version of the flash does support it, so that might be worth upgrading to that.

20:03 <mwk> hmm

20:03 <mwk> the controller does seem to attempt such a reset already, though

20:03 <mwk> it always sends a dummy 0xff command and then a dummy 0xab command on startup

20:05 <tnt> Oh I mean disabling it at runtime, not on reset.

20:05 <mwk> yes

20:06 <mwk> but changing the config register should restart the controller state machine

20:07 <mwk> softreset <= !config_en || cfgreg_we;