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<tpw_rules>
whitequark: remember your idea of a boneless port for loading the firmware? i think that would be useful actually for one boneless to load another without having to have a mux on its memory bus
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<whitequark>
tpw_rules: alrighty, ping me tomorrow
<tpw_rules>
btw uh if they're not on your queue, the uart in nmigen-stdio is definitely bit reversed, and making the assembler warn of register in place of a constant and also constant in place of a register
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<pepijndevos>
daveshah, do you think the lenght of the frames is stored somewhere? Or more likely that it just reads until it finds the long string of ffff at the end
<daveshah>
More likely frame length is baked into the chip
<daveshah>
Because its a fundamental design constant of the fpga
<pepijndevos>
sure, but so is the number of frames, which is stored in the bitstream.
<pepijndevos>
I'm trying to make my parser a bit more robust so it can actually handle GW1N-1, which doesn't have the ffff padding at the start of each frame.
<daveshah>
The number of frames is there to allow split or partial loads
<daveshah>
Whereas, whole frames always have to be loaded so the bits per frame would never change
<pepijndevos>
Ah, I guess that's what you'd use the init address for? So you can just start in the middle and write a few frames
<pepijndevos>
Is this what partial reconfiguration is about? (I guess it involes a few more things)
<daveshah>
Yeah, this is how partial reconfig on ECP5 works
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