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<ZirconiumX> ZipCPU: Additionally, Figure 4.1 from the spec is confusing; R1/CMD is specified as 8-bit wide, but only covers bits 0:4 of the diagram
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<ZipCPU> ZirconiumX: No, that section of the register is 8-bits wide
<ZipCPU> The command sent to the SDCard will be those 8-bits, the 32-bits from the data register, a 7-bit CRC followed by the stop bit
<ZipCPU> Nvm, looking closer I see the problem
* ZipCPU should've read ZirconiumX's comment a bit closer
<ZipCPU> Ok, problem wasn't that the field was 8-bits wide, but rather that the unused field wasn't big enough
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<ZipCPU> Ok, check now. Should be fixed: https://github.com/ZipCPU/sdspi/blob/dev/doc/spec.pdf (Page 10)
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<tpw_rules> :O my allocator works!
<tpw_rules> i'm a real computer scientist now
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<OmniMancer> :O
<GenTooMan> you can allocate random blocks of memory and then delete and reallocate them?
<tpw_rules> no, register allocator
<tpw_rules> it uses Graphs
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<GenTooMan> local variable allocation then?
<tpw_rules> yeah
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<GenTooMan> that's fun to do. It's definitely not as simple as the "use the stack" idea. It is however much faster. I've seen several compilers do it wrong and ... well let's just say bad optimization is possibly worse than no optimization.
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<GenTooMan> Oh yeah congrats on your success. :D
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<tpw_rules> it's for wq's boneless so i don't have to think about registers anymore
<tpw_rules> i really agree with her vision that a good assembler should have an allocator too
<tpw_rules> it's still missing some features, like being able to spill anything and to understand the calling convention
<tpw_rules> but it works, very surprisingly
<tpw_rules> (and once again reinforced my belief that papers and "the literature" are kinda useless)
<GenTooMan> It's always good to see what people are thinking. Unfortunately papers have become like sports. They compete using their mind as the game tool instead of their hands and feet. However the result seems mostly the same, unproductive use of time.
<tpw_rules> if i wanted to say it positively, i would say that actually implementing something is the highest form of understanding
<tpw_rules> but it's frustrating coming across like 10 papers and class slideshows that all miss the same bit
<GenTooMan> that bit you need to complete your task at hand?
<tpw_rules> yeah. and it always turns out that they've elided something or that you need to just do it slightly differently for your application
<tpw_rules> anyway other positive is that my allocator is already better than me. i ran through a real life routine with 75 instructions. i allocated 7 registers, it did it in 6
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<GenTooMan> and you tested the code I assume as well?
<GenTooMan> now their is just boneless C ... and we are good to go ... LOL
<tpw_rules> yeah
<tpw_rules> eh, C is lame
<tpw_rules> with bones or not
<OmniMancer> boneless Rust :P
<tpw_rules> i feel like asm with a register allocator and an expression engine is gonna be boneless C
<GenTooMan> sort of like PDP11 assembler. You could easily write entire applications in that. It was very weird to do so also. Felt rather retro doing that.
<OK_b00m3r> GenTooMan: asm was an applications languge for a remarkably long time. into the 1990s at least.
<OK_b00m3r> probably still hangs on.
<tpw_rules> there's still weirdos that use it as such
<GenTooMan> I wrote ASM translators for several processors. It was weird but it was faster than rewriting 81 programs.
<tpw_rules> https://www.grc.com/default.htm like this guy
<OmniMancer> Boneless Forth
<tpw_rules> i don't think forth has any bones
<GenTooMan> each has it's uses. I use assembly when the compiler generates crap code, or intrinsics either way. Hey let's all think in reverse polish notation!
<OK_b00m3r> any minute now someone will mention the spineless
<OK_b00m3r> g machine
<cr1901_modern> Boneless p-code interpreter
<tpw_rules> only time i've used assembly on a pc in recent memory is i did a couple image scaling routines in ARM NEON
<tpw_rules> (which was very pleasant)
<GenTooMan> let me clear my mind of that (gun fires)
<OK_b00m3r> tpw_rules: Yeah, honestly i enjoy it any chance i get (not x86 though)
<tpw_rules> out of the 10 assembly languages i know, none of them are x86. closest relative is gameboy-style z80
<GenTooMan> actually using the old mmx code wasn't so bad.
<GenTooMan> the mmx made sense but not the x86 LOL
<GenTooMan> Wow.. Z80. that's ... ancient history.
<OmniMancer> well the gameboy CPU isn't very Z80
<GenTooMan> It's kind of sort of Z80 like? :D
<tpw_rules> yeah, it's a bit strange why it gets called that
<tpw_rules> it's a linear combination of a z80 and an 8080
<OmniMancer> its more very slightly extended 8080
<tpw_rules> but more 8080 than z80
<OmniMancer> it has the bit manip instructions from z80 but nothing else that was extended
<tpw_rules> like the extra register file
<OmniMancer> it has no in or out and does everything with MMIO
<OmniMancer> no extra register file, no IX or IY
<tpw_rules> but it has special in and out instructions for the mmio area
<OmniMancer> yes it has special shortcuts for reading the top 256 bytes of the address space
<tpw_rules> i wonder why it ended up like that. was it patents like the nes?
<OmniMancer> who knows, the lack of in and out make sense
<OmniMancer> since it doesn't separate IO bus and memory bus
<OmniMancer> being embedded in a larger chip
<GenTooMan> Well in Japan their is a city named USA for similar reasons.
<GenTooMan> it's possible they were skirting copywrite laws.
<tpw_rules> there's exactly one transistor missing out of the 6502 in the nes to avoid a patent, but the gameboy cpu is a serious revamp
<tpw_rules> comparatively
<GenTooMan> Japan is never afraid of doing something wildly different at least.
<GenTooMan> likely having a semi custom IS was advantageous to them.
<OmniMancer> The gameboy ons is a Sharp part apparently
<OmniMancer> oh hey attosoc takes exactly 50% of the LUTs that I have exposed in the generic backend :P
<OmniMancer> not quite
<OmniMancer> 4906/9800
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<GenTooMan> you keep reminding me of things I should do OmniMancer.. stop it LOL
<tpw_rules> huh he left
<tpw_rules> anyway uh i think the gameboy cpu is just manufactured by sharp. the die has all the video and sound stuff on it too
<tpw_rules> ricoh made the cpu and ppu for the nes and snes but i don't think they were especially involved in designing them
<GenTooMan> Well considering Japan highly complex culture ... it's not a surprise at all.
<cr1901_modern> I don't have a link handy, but the CPU for the SNES was IP purchased from WDC- i.e. no difference from the 65816 ICs that WDC was putting out in the late 80s.
<tpw_rules> yeah the actual core was (and so was almost the NES's) but it's still on a nintendo custom die with the controller port stuff and like the system dma engine
<tpw_rules> so idk, did sharp already have this weird 8080 available?
<GenTooMan> LOL it's hard to know honestly. If we did know what good would it do us? Anyhow that's what I am thinking.
<GenTooMan> I need sleep so I'll work on doing that.
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<ZirconiumX> ZipCPU: better, thank you!
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<OmniMancer> GenTooMan: what sorts of things do you need to do?
<OmniMancer> tpw_rules: sorry I had other things pulling me away
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<OmniMancer> daveshah: is there a reason for nextpnr to generate the packer VCC cell with a LUT init of all 0s except a single 1?
<ZirconiumX> OmniMancer: a single-bit inverter, maybe?
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<OmniMancer> but it has 32 (even though the LUT only need 16) bits written out
<OmniMancer> wouldn't you want a LUT with all 1's so it outputs high regardless of input?
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<OmniMancer> daveshah: nextpnr doesn't have directionality on wires does it?
<daveshah> No, only on pips
<OmniMancer> and pips do have a direction?
<daveshah> Yes, always, from source to dest
<daveshah> (bidir pips are implemented with two unidir pips)
<OmniMancer> okay
<OmniMancer> I feel like I have somehow convinced nextpnr that there is a connection from the middle of an interconnect wire to something where the database only has the end of that wire
<OmniMancer> since it gives me some pips that are not possible
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<OmniMancer> hmmm, though my list of pips does include that impossible connection for the PIB block, so maybe it works in the PIB block I used for fuzzing :/
<OmniMancer> hmmm for some reason there is a duplicate of another route there with that name, perhaps the tools were being weird in that block or I have a bug
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<OmniMancer> I wonder if this is because that pib block is on the edge of the device so doesn't have neighbours on two sides so gets some strange treatment
<pepijndevos> OmniMancer, what happens in Gowin that at the edges the wires wrap around
<pepijndevos> IIRC it's similar on other FPGAs
<OmniMancer> pepijndevos that would make some sense with what I am seeing
<OmniMancer> kind of
<OmniMancer> it just means it probably needs some special handling
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<OmniMancer> This is most inconvenient though :/
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<OmniMancer> daveshah: are the interconnect to interconnect pips the same in every tile in ecp5?
<daveshah> Yes but there are some oddities in naming around the edges
<daveshah> Trellis normalises them for the database
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<OmniMancer> what do their names usually look like?
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<OmniMancer> I have noticed that there are some cases with two different names producing the same bits
<OmniMancer> daveshah: I think I might need to make the interconnect fuzzer try several tiles and pick only arcs that produce bits in all of them
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<ZirconiumX> ZipCPU: Another point of confusion: the 8-bit-wide R1/CMD field mentions that it contains the R1 response, which is 48 bits long and has a 32-bit status field
<ZipCPU> No, just the first 8-bits of any response. For SPI mode, that's often all there is
<ZirconiumX> "Code length is 48 bits. The bits 45:40 indicate the index of the command to be responded to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits." - Physical Layer Simplified Specification v6.00
<ZirconiumX> For "4.9.1 R1 (normal response command)"
<ZipCPU> Yeah, that's the SDIO half of the spec. SPI is a touch different
<ZipCPU> Here, check out Format R1. It's only 8-bits
<ZipCPU> Fig 7-9: R1 Response Format
<ZirconiumX> Right, thank you
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<tpw_rules> ZirconiumX: did you miss elm-chan's docs?
<ZirconiumX> I did read them :P
<tpw_rules> alright. i've never actually read the official specs, only that page :P
<ZirconiumX> ZipCPU: Since you know much more than me about this, should the SD card I/O be insulated by a flip-flop synchroniser chain?
<tpw_rules> i would estimate no, because it's clocked. i didn't do it for my spi flash engine
<whitequark> you have to consider the timings of the SD card and the FPGA
<tpw_rules> that said, i didn't hook it directly to any logic, which i think is what whitequark is trying to get at. it goes directly to a flip flop
<whitequark> no
<whitequark> not quite
<whitequark> the SD card has a clock-to-out delay, and the FPGA has setup/hold constraints
<whitequark> so if you're clocking the FPGA fast enough, and the SD card is slow enough, that the SD card changes its output right when the FPGA is trying to capture it (on the next cycle), that could cause issues
<whitequark> i hit a very similar bug on Glasgow, with the FX2
<whitequark> and had to capture on negedge
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<ZipCPU> ZirconiumX: tpw_rules and whitequark have the right answer. There's no need to run the incoming data through a 2FF synchronizer since it's clocked, and you know when it changes
<ZirconiumX> Right, thank you
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<tnt> I was looking at #361, but is there a reason objcopy isn't used to embed binary into the elf rather than compiling a huge C file ?
<whitequark> windows?
<whitequark> msvc doesn't have objcopy