verilog and vhdl were originally created to write sim models while the actual design files were made by a different team with vector graphics programs, synthesis was tacked on later. this doesn't explain why it's gotten *worse* though, synthesis has been an established use case for decades now
systemverilog was made by people who looked at c++ and thought, "what a honkin' good idea"
might be a C++ thing "we'll add all the features, if you don't like them don't use them"
that's all the explanation i need
Yea, but, like... IIRC VHDL was designed by some commitee, so just wondering if Verilog was just some rando at some company who mad a thing they needed.
it seems the global clock spine is actually 8 bits high in the bitstream, while the numbers I was using as a proxy for position in the bitsteam only jump by 2 at them