<tnt>
The "FIFO" has no status (valid/empty/...). The _write_ clock is wired to sgmii_pclk and the _read_ clock is wired to sgmii_rclk.
<tnt>
I don't see how that's useful in any way.
<omnitechnomancer>
tnt: what does the immi_ready mean?
<omnitechnomancer>
or is it lmmi
<tnt>
lmmi lattice memory mapped interface
<tnt>
some bus used to expose config registers in hard ips.
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<omnitechnomancer>
ah
<tnt>
What I don't get is what the fifo is doing at all. The data coming off the "deserializer" are at the "sgmii_rclk" rate (i.e. recovered clock). and not synchronous to whater "pclk" is (which seems to be a local 125 MHz clock, but that's obviously not synchronized to the recovered clock and so can/will drift).
<omnitechnomancer>
indeed
<tnt>
And then they re-read from that fifo (which AFAICT is now filled with half garbadge from sampling the deserializer output with an unrelated clock) at the recovered clock rate. Why not just output the deserializer output directly !?
<omnitechnomancer>
you would think it would have a ready signal so you can stop reading if it's empty :/
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<tnt>
no one ?
<omnitechnomancer>
I cant think of a reason, unless the diagram is lying
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<tnt>
well, I checked the simulation model too ... and the PCS ip core in the radiant library.
<omnitechnomancer>
weird :/
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<daveshah>
PCLK is fed with RCLK after going through the global clock network
<daveshah>
At least this is more or less what ECP5 SERDES look like
<daveshah>
This effectively compensates for the global buffer delay on RCLK to soft logic
<daveshah>
Without the FIFO logic (clocked by the global buffer output) would be sampling with a phase shift vs RCLK directly
<tnt>
huh, but I'd still expect the pclk to be on the read side of the fifo and not the write side.
<tnt>
also, from the PCS IP from radiant, they definitely just feed the output of a PLL that's unrelated to the recovered clock.
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<tnt>
They actually feed the same clokc as into the SREFCLK (reference clock) port.
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