<OmniMancer>
perhaps I should convert to this form at some point
<OmniMancer>
I think the IO doesn't need it since I think they are in the same row/column as the routing for them, so only ever offset in one directions
<OmniMancer>
but unsure if other things will be less easy
<OmniMancer>
daveshah: I am not sure I entirely understand the naming of the intertile routing signals in trellis
<daveshah>
I never really figured out the meaning either
<daveshah>
I just normalised the naming lattice uses
<OmniMancer>
ah okay, the Anlogic ones seem much more intuitive
<OmniMancer>
what exactly gets normalised there?
<daveshah>
Names at the edge
<daveshah>
But I more just took a lot of samples and found patterns rather than really tried to work out all the different numbers
<OmniMancer>
so I guess that is somewhat similar to the issue I saw with extra pips existing near the edges
<OmniMancer>
so does the routing graph in lib trellis do anything to match up the wires between tiles with the arcs that use them?
<daveshah>
Yes, it combines all wires using the relative coordinate system
<daveshah>
Wire A in a tile and N1_A in a tile below will be combined
<OmniMancer>
are those wires stores with some realtivised naming in the db?
<OmniMancer>
ah
<OmniMancer>
and that happens for tiles which have multiple associated routing blocks?
<daveshah>
It doesn't really consider routing blocks
<daveshah>
Wires and pips are effectively converted back to relative coords to store in the db
<OmniMancer>
I guess I mean so far for me the only inter tile wires are the actual nesw wires
<OmniMancer>
which are already named in a form of relative coords
<OmniMancer>
in that they are named as a direction a span and whether they are the beginning, end or middle
<OmniMancer>
so for those I can work out which wire they are systematically, or I was just adding fake pips in the generic backend which took ages
<OmniMancer>
so e6end0 would be the first eastgoing 6 span wire from 6 tiles west of this one
<OmniMancer>
perhaps these should be normalised into some kind of W6_e6beg0 or something in the DB to make the merging easier later
OmniMancer has quit [Quit: Leaving.]
<SpaceCoaster>
Thanks for the tweaks, ran through all the fuzzers. I didn’t realize how many wires and muxes a FPGA has. What does the beg in the w2beg7 name stand for?
<whitequark>
FPGAs are like, mostly wires and muxes
<mwk>
SpaceCoaster: beginning
<mwk>
where the net driver is
<mwk>
or, well, segment driver
azonenberg_work has quit [Ping timeout: 245 seconds]
<SpaceCoaster>
Watching a fuzzer do the luts in seconds then grind through the routing config for hours brought it home.