<TD-Linux>
they describe "edge positioning logic". basically I assume it's a delay line with many taps, and the tap positions are adjusted with some sort of pll
<whitequark>
like xilinx s7 calibration logic?
<whitequark>
use a low speed but precise clock, count delay line pulses, adjust as neede
<whitequark>
sort of like a pll but not quite
<TD-Linux>
yeah I think it's like that, except the s7 has one tap that moves, and this has 32 taps that move
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<omnitechnomancer>
daveshah: now I must steal libprjoxide :P
<tnt>
Arf, it's in rust :/
<daveshah>
Is that a problem?
<tnt>
My experience with rust on gentoo has been annoying. Like it takes forever to build the toolchain and every update rebuilds every module which agains takes forever and blocks my laptop for half a day to a day ...
<tnt>
so I've been avoid it tbg.
<daveshah>
I've had no problems with it on Arch, even using rustup to get nighties
<daveshah>
*nightlies
<daveshah>
I can't see rust being that much of a PITA on any modern Linux distro as it is a dep for Firefox isn't it?
<tnt>
daveshah: Heh I actually switched from firefox to chrome for that reason.
<tnt>
(and because in addition to rust they also made nodejs a deps ... and I didn't want to deal with _two_ annoying deps)
<omnitechnomancer>
sounds like a reason not to use Gentoo to me
<omnitechnomancer>
daveshah: Gentoo insists on building everything locally
<tnt>
well not using gentoo wouldn't help me to not have nodejs and firefox.
<daveshah>
But rustup would probably bypass that?
<omnitechnomancer>
rustup should work fine
<omnitechnomancer>
use rustup
<omnitechnomancer>
rustup is good
<daveshah>
In any case I think rust would have become a dependency for open source FPGA stuff at some point anyway
<daveshah>
and removing Boost and any end user need to link against python (bba export when done will be pure rust) will probably have a net positive impact on ease of build
<omnitechnomancer>
indeed
<omnitechnomancer>
though how has the pyo3 experience linking to python been?
<daveshah>
Not bad, although as pyo3 seems to need nightly rust I'd rather have it as a dev-only dependency
<daveshah>
The bba export will probably be faster in pure rust and I don't see any real need for python there anyway though
<omnitechnomancer>
ah yes that is a bit annoying
<omnitechnomancer>
And yes I think most of the work is dealt with building the graph anyway the rest is just shuffling things around and printing out the bba format
<daveshah>
The idea is to get rid of most of the building the graph too
<daveshah>
and do some proper pure-dedup flow
<daveshah>
but that needs some more thought
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<omnitechnomancer>
Well yea, I need to get around to finishing trying to morph libtang to build the unique types directly
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<omnitechnomancer>
daveshah: when combining LUTs on an ECP5 how large can they combine to?
<daveshah>
Up to a LUT8 (2 slices) I think but I've only implemented up to LUT7 as there is little non wasteful use of the LUT8 mode
<omnitechnomancer>
so you can make a LUT5 from one slice yes?
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<omnitechnomancer>
And then combine two slices to make one LUT6, how do you get a LUT7 and LUT8?
<daveshah>
Oh sorry I meant two tiles for a LUT8
<daveshah>
yeah one slice for a LUT5, two for a LUT6 and four for a LUT7 (1 tile)
<omnitechnomancer>
where does the MUX live for using the whole tile?
<omnitechnomancer>
and then I assume LUT8 is two tiles in LUT7 stapled together?
<omnitechnomancer>
The FXA and FXB inputs are to the combining MUX?
<omnitechnomancer>
ah yes I see the diagram in the datasheet
<omnitechnomancer>
and the M0 and M1 inputs are used to drive the combining muxes?
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<daveshah>
Yes M0 is the select for the LUT5 mux, M1 is for the 6/7/8 mux (which indeed selects FXA and FXB)
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<omnitechnomancer>
Are the FXA and FXB connections routable or fixed?
<daveshah>
They are fixed connections between slices
<azonenberg>
Interesting
<azonenberg>
In xilinx land, the luts are paired 5-input luts (same input, separate outputs) that are normally combined via a mux to a single 6-to-1 lut
<azonenberg>
Then there's two F7MUXs per slice which each can combine two lut6s to a 7 input function
<azonenberg>
and one F8MUX to combine four lut6s (an entire slice) to an 8-input fnuction
<azonenberg>
afaik there's no support for wider functions, you have to just combine slices with lut logic
<mwk>
they're called MUXF7 and MUXF8
<mwk>
and Ultrascale also has MUXF9
<daveshah>
Well the primitives are MUXF7 and MUXF8
<daveshah>
the bels are F7MUX and F8MUX
<daveshah>
for some reason
<mwk>
the LUTs are not really paired 5-input LUTs, they're a single LUT6 where you can access the full LUT and the bottom half-LUT
<daveshah>
Oh, cursed primitive time, looks like the CrossLink NX has a DDR register mode
<daveshah>
It's not really documented but its a setting called REGDDR
<mwk>
which you can use as two 5-input LUTs by hardwiring the 6th input to 1
<mwk>
and yeah, there's nothing wider
<daveshah>
and it sets two config bits, one is normally used for rising edge clock and the other for falling edge clock
<daveshah>
I haven't any hardware to try yet but it seems fun
<omnitechnomancer>
The sim model for the eagle implies there might exist the extra connections to produce larger LUTs using the other MUX in the slice, but they arent actually connected anywhere in the sim model
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<marex-cloud>
mithro: so where are you now?
<marex-cloud>
mithro: the next talks look boring
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<omnitechnomancer>
marex-cloud: you are at 36c3? I hope it is enjoyable.
<marex-cloud>
Its ok
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<mithro>
marex-cloud: I'm at the hardware hacking assembly in the corner to the right of the stage near the kit tables