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<omnitechnomancer> SpaceCoaster: I have not worked out how, you can always pipe its stdout somewhere else but I havent worked out how to get it not to make log files
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<sensille> what do i need to program an ecp5? can i use a xilinx or altera programmer? or an avrispmkii?
<tnt> anything that can play a svf file allows jtag programming.
<tnt> alternatively, depending on the board, you might be able to just program the flash directly (using spi) and then let the ecp5 reconfigure itself on the next boot.
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<sensille> via jtag i mean. so i need to find out if there's an svf handler for xilinx or altera programmer
<sensille> or the avrisp
<daveshah> I think OpenOCD supports the Xilinx programmer and maybe the Altera one too
<sensille> interesting, thanks
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<mwk> whitequark: ping about q3k's issue above
<whitequark> which?
<whitequark> nvm found it
<whitequark> ugh
<mwk> agreed
<whitequark> Nina raised this issue long ago
<whitequark> it's not fixed in nmigen because there was no ram_style attribute
<whitequark> and this is why I am advocating so much for having one
<whitequark> (I would have got around to implementing it eventually... I came close to doing so a month ago but got higher priority stuff to do)
<whitequark> q3k: mwk: IMO the transform done by the Xilinx toolchain is unsound since it results in sim/synth mismatch
<mwk> I agree
<whitequark> but arguably the whole idea of having synthesizable verilog is unsound instead
<mwk> hm
<whitequark> instead of explicitly specifying the memory behavior you're trying to get inference to pick the right one, HLS-style
<mwk> wait, what "xilinx toolchain" are we talking about here? ISE? Vivado? yosys+ISE/Vivado?
<whitequark> ISE and Vivado
<mwk> so they're broken as well? fuck
<whitequark> yes
<whitequark> yosys is actually doing the "right" thing AFAICT
<mwk> no
<whitequark> (unless it subtly differs from Vivado in some way)
<whitequark> Xilinx gives you some "coding guidelines" that result in correct logic being inferred
<whitequark> using anything other than the suggesting Verilog "macros" is effectively UB according to them
<mwk> yosys clearly still converts async read port to sync read port
<whitequark> hm
<mwk> the only thing preventing it from doing it now in q3k's case is that the addr register is initialized
<whitequark> I don't claim to have a lot of insight into memory inference here, and what I do know isn't paged in
<daveshah> Address registers will create a transparent read port
<whitequark> if you want me specifically to chime in at JF or something I could try to study this in detail but I trust you'll figure it out
<daveshah> Yosys will not make soft transparency logic for multi clock BRAMs now
<whitequark> daveshah: wait, for any multiclock BRAMs, or for multiclock BRAMs between ports?
<whitequark> this goes back to my "port groups" suggestion...
<daveshah> Multiclock between ports afaik
<whitequark> ah ok
<whitequark> regarding port groups, see the links in
<mwk> whitequark: I pinged you because it involves a migen macro and I wanted to ask you whether this thing is intended to synth to BRAM or not
<mwk> but the bug you linked answers this
<mwk> thanks
<whitequark> ack
<mwk> so — the question now is what to do about the yosys pass doing this unsound transform
<mwk> which is memory_dff
<mwk> IMO the transform should be nuked, or at least stuffed with loads of checks that make it actually sound (ie. single clock for whole BRAM, no enables that could screw up semantics, ...)
<whitequark> btw if you are looking into this...
<whitequark> could you please fix transparent ports with RE?
<mwk> you're welcome to chime in at JF, but if you don't want to bother, I'll handle this myself
<whitequark> right now they're FUBAR
<mwk> RE?
<whitequark> read enable
<whitequark> write_verilog emits invalid verilog for them
<mwk> I don't know how they're even supposed to behave
<whitequark> well, if the \EN input is low, the value does not change
<whitequark> are there other possibilities?
<mwk> I mean I'm not clear how transparent read ports are suppoed to behave
<mwk> enable semantics are clear
<whitequark> oh hm
<whitequark> I mean I think the semantics is the same whether they're transparent or not but now I'm thinking about how the soft transparency logic should work
<whitequark> the DFF is inside the BRAM, so you need a... latch after it
<mwk> this never ends well
<whitequark> I think I know how to do this
<mwk> would a mux suffice?
<whitequark> hmm
<Morn_> is a transparent read port one that updates without clock cycle delay?
<whitequark> yes
<mwk> that sounds like async read port
<whitequark> that's an easy and twice incorrect way to implement it
<mwk> transparent is sync port that, if a value is written to the same address in the same clock cycle, reads the new value as opposed to the old value
<mwk> (unelss I misremembered this badly)
<whitequark> you're correct
<Morn_> so still synchronous and with one cycle delay?
<mwk> yes
<mwk> the only difference is what happens when waddr == raddr
<whitequark> basic soft transparency logic works like this: you add a mux between rdata and wdata, selecting on waddr == raddr
<Morn_> i see, interesting
<whitequark> this breaks down if you add enables
<whitequark> read enable specifically
<Morn_> how?
<whitequark> because a disabled read port will still change state whenever waddr == raddr
<mwk> hmm
<mwk> have two extra registers
<Morn_> could you do that check not before the waddr = raddr mux?
<mwk> wdata, and waddr == raddr
<mwk> have a mux after the registers
<mwk> connect read enable as clock enable to both registers
<whitequark> does that actually work?
<Morn_> are you talking about a register-based memory or like an SRAM/BRAM?
<mwk> I think so
<whitequark> BRAM
<mwk> Morn_: BRAM
<mwk> something like this?
<whitequark> mwk: doesn't this delay rdaddr == wraddr by one cycle?
<whitequark> compared to current logic
<mwk> what current logic? write_verilog?
<whitequark> soft transparency logic insertion
<mwk> b
<mwk> but logic where?
<whitequark> in yosys
<whitequark> hm
<whitequark> hang on
<whitequark> i might be misunderstanding
<mwk> you mean memory_bram?
<whitequark> yes
* mwk looks
<whitequark> wait, it ... seems to do exactly what you're suggesting?
<mwk> that sounds good
<whitequark> hm, let me double check
<mwk> hrm, wait
<mwk> ohh
<mwk> Mux has the selector as the *last* argument
<mwk> nvm
<mwk> it seems to be missing support for read enable though
<mwk> yeah
<mwk> and to make it support read enable, you'd need to change the addDff to addDffe
<mwk> for both transp_en_q and mktr_wrdata_q
<mwk> which would require unsharing mktr_wrdata_q for the case with multiple read ports
<mwk> (but that's unavoidable)
<whitequark> re Mux: that mux is hella weird
<mwk> it's a mux that's really an And
<whitequark> wen ? (waddr == raddr) : 0
<whitequark> yes
<whitequark> why
<mwk> no
<mwk> (waddr == raddr) ? wen : 0
<mwk> because wen is a multi-bit value
<mwk> (byte enables etc)
<whitequark> oh
<whitequark> ok makes sense
<whitequark> I think a worse problem is what to do with RE+TRANSPARENT ports in $mem and write_verilog
<mwk> yes
<mwk> I'm afraid I don't have a good answer to that question
<mwk> I mean, we could do the same thing as memory_bram does in write_verilog and hope that whatever parses our code can figure out how to convert it back
<mwk> but given how much BRAM inference sucks everywhere, I'm not hopeful about it
<mwk> whitequark: this pattern doesn't have read enable though
<mwk> which is because it's about a single port
<whitequark> right
<whitequark> it's about two ports
<whitequark> read and write
<whitequark> oh wait
<whitequark> a single r/w port
<mwk> yes
<whitequark> right
<whitequark> that's a pain
<mwk> I wonder if Xilinx would even recognize it if you used different r/w addresses
<whitequark> they have really weird handling of collisions
<whitequark> I think I forgot to write down the exact details :/
<whitequark> I've asked azonenberg to explain it before, I think?
<mwk> you asked me about it
<mwk> unless we're talking about different things
<mwk> and my guess about the weirdness is that they're implementing WRITE_FIRST not by adding muxes but by manipulating relative timings of write strobe vs read strobe
<whitequark> could have been you
<whitequark> right, so, hm
<whitequark> oh, I asked azonenberg about write-write collisions
<whitequark> which are always undefined IIRC, which makes sense
<mwk> yes, reasonable
<whitequark> was there something weird about read-write collisions too?
<mwk> I think so?
* mwk opens documentation
<mwk> alright, so for single clock, UG473 (series 7) says:
<mwk> When one port performs a write operation, the write operation succeeds; the other port can reliably read data from the same location if the write port is in READ_FIRST mode. DATA_OUT on both ports then reflects the previously stored data.-
<mwk> If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the DATA_OUT on the read port would become invalid (unreliable). The mode setting of the read-port does not affect this operation.
<mwk> so the *read behavior* specified for the *write port* decides whether the read on the other port works right
<mwk> which, incidentally, means you cannot really support transparent simple-dual-port memories, if I understand this correctly?
<mwk> also uh
<mwk> Spartan 6 READ_FIRST sounds hilariously bad
<mwk> (for two async clocks, from UG383 page 15)
<whitequark> right
<whitequark> so they're trying to play with timing of write strobe
<whitequark> and as a side effect this completely defines their inter-port collision behavior
<whitequark> right?
<mwk> well
<whitequark> the read strobe is fixed, and the timing of the write strobe is determined by the READ_FIRST/WRITE_FIRST setting
<mwk> "then the DATA_OUT on the read port would become invalid (unreliable)"
<mwk> the does not sound completely defined
<mwk> but otherwise yes
<whitequark> i meant defined in a colloquial sense
<whitequark> "determines"
<mwk> agreed
<mwk> I wonder why, btw
<mwk> so somehow the strobes on the two ports are slightly misaligned in such a way that it works fine for READ_FIRST mode, but not for WRITE_FIRST?
<ZirconiumX> whitequark: idly browsing through prjbureau and noticed some typos in the NORx cells (output wire is QN, but assign goes to NQ)
<mwk> hmm, Virtex 6 has the same weird async high address bits collision behavior as Spartan 6
<mwk> I guess this translates to "don't use READ_FIRST when the two ports have different clocks, and don't use WRITE_FIRST if they have the same clock"
<mwk> wonderful mess
<mwk> why is everything horrible
<gruetzkopf> aaaah
<gruetzkopf> :xilinx_
<ZirconiumX> I feel like I'm insufficiently educated on how Intel stuff works, and I appear to be the abyss domain expert here
<mwk> Virtex 4 and Virtex 5 documentation says the same as Series 7 (ie. no weird high address bit behavior)
<mwk> Spartan 3, on the other hand, says that using WRITE_FIRST or NO_CHANGE on a write port invalides the data read on the opposite port, but never mentions this only happens when they access the same cell
* mwk wonders if that's an oversight, or if the hardware is *that* horrible
<mwk> and Virtex 2 again matches Series 7
<mwk> so probably an oversight
<omnitechnomancer> oh my
<mwk> alright
* mwk has reached her quota for broken software, broken hardware, and broken languages today; goes to grab a coffee and forget all about blockrams
<whitequark> heh
<whitequark> weirdly enough, strange broken shit helps me recharge
<whitequark> the stranger and brokener, the better. this is why i end up with so many 8051s i guess
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<gruetzkopf> is the ti cc2531 in your collection yet? (usb FS, 2.4GHz radio, commonly used for 802.15.4 and zigbee)
<whitequark> docs collection? or cursed shit collrection?
<gruetzkopf> latter, docs are public
<gruetzkopf> the radio controller is "interesting", you can pre-prepare command lists channel-controller style
<mwk> whitequark: I don't mind strange broken shit, but this grew way too large for a quick fix and risks swapping out the stuff I'm working on now, for which I just managed to break a months-long procrastination streak
<gruetzkopf> (all code i've ever seen for these radio 'hand-feeds' single commands though)
<gruetzkopf> (radios from that family also exist as spi slaves) </otY>
<whitequark> that actually sounds real neat
<whitequark> I remember trying to use ti cc* chips as a little baby who couldn't RF
<whitequark> unsurprisingly i never got any of them working because at the time i didn't have any pocket money and trying to do toner transfer for relatively fine pitch QFNs is hard
<whitequark> and i think it was before the really cheap PCB fabs took off anyway
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<gruetzkopf> premade usb dongles with those are cheap, i can have the chinese drop-ship some if you want
<gruetzkopf> ti cc1100 is _the_ classic sub-ghz radio, yeag
<whitequark> hmmm
<whitequark> how do the dongles work
<whitequark> oh it's like nRF24LU1
<whitequark> which i still have to bring up
<whitequark> uh, what happened to that connector
<whitequark> and what are DC/DD?
<gruetzkopf> debug clock, debug data
<gruetzkopf> yet another two+reset pin interface
<gruetzkopf> (and thats some "nodejs is the ideal embedded runtime" persons website)
<whitequark> ugh
<whitequark> i guess i could write a glasgow applet for it
<whitequark> of *course* cc2531 has a 8051 inside
<gruetzkopf> which is why i mentioned it (8051)
<whitequark> is the interface completely proprietary?
<gruetzkopf> there are (horrible) implementations of that protocol for arduino and wiringpi (ugh)
<gruetzkopf> still looking if it's publicly documented by ti
<whitequark> link?
<whitequark> just gonna skim it
<whitequark> nvm it's described
<gruetzkopf> ooh
<gruetzkopf> host clocked, data sampled at posedge
<whitequark> yeah it's just two wire spi
<whitequark> pretty uncursed if you ask me
<whitequark> bit similar to microwire
<whitequark> yeah, i should implement microwire for glasgow, and get this more or less for free
<whitequark> i feel like i ought to write some sort of "universal serial core"
<whitequark> with a SERDES-style pipelined interface and capability to do half/full-duplex single dual and quad transfers
<whitequark> eSPI would work with it too
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<kc8apf> That's the only simple part of eSPI
<whitequark> indeed
<whitequark> fun fact: when i talked about eSPI on twitter, its designer DM'd me
<kc8apf> Nice
<kc8apf> Speaking of 8051, I want to get back to playing with the JMedia JMS583 USB 3.1 to PCIe bridge
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<cr1901_modern> I need to re-learn 8051 (after not having touched it for 8 years) for an upcoming project... whee...
<whitequark> sdcc master now even has C2X features
<whitequark> pretty impressive
<cr1901_modern> Yea, that was my plan- checkout sdcc and use the upstream assembler
<whitequark> hm, is there an issue with sdas8051?
<cr1901_modern> No, tou just mentioned a while back that the upstream assembler got much better ergonomically, though that was months ago. sdcc may have released a version since then, making whether I use upstream or not irrelevant.
<whitequark> ah interesting
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