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<GenTooMan>
omnitechnomancer oh ... I suppose if they are doing something "easy" but sluggish that would do it. It makes a bit more sense suddenly.
<omnitechnomancer>
GenTooMan the adaptor works by you send it an array of bits to set the various JTAG signals to AFAIK
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<anticw>
omnitechnomancer: most software sucks, sorry :(
<GenTooMan>
indeed. it takes real effort to make good software. Unfortunately reality is most people don't want to put the effort in.
<OK_b00m3r>
or can't get budget for it
<diamondman>
I am happy to see my documentation being used on the Platform Cable
<GenTooMan>
I'm happy documentation is used period... really!
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<OK_b00m3r>
^
<OK_b00m3r>
it's a miracle
<omnitechnomancer>
daveshah thinking about it I think there are two cases for inter tile wires, the routing fabric wires which might go to tiles that don't exist because of the edge of the fabric, and then the case for tiles which are really larger than one pib and so have fixed connections into tiles with other co-ords
<omnitechnomancer>
In the latter case the source tile is always present so referencing the wire in that tile should be fine even relatively
<omnitechnomancer>
In the former case some mechanism is needed to allow the wire to exist even if the tile doesn't
<omnitechnomancer>
Would having a separate array for routing wires and using a higher order bit to signal which place to find the wire work? Then add routing wires even outside the usual fabric
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<kc8apf>
I see I'm not the only fighting programming tools today. Couldn't get sp605's built-in JTAG USB thingy to work under win 10.
<kc8apf>
Actually used SystemACE today because......it worked
<omnitechnomancer>
Perhaps have a separate interner for intertile wires, and those wires "exist" in every tile
<omnitechnomancer>
what does nextpnr use the method to get all wires on the device for?
<omnitechnomancer>
having to iterate over all wires makes things slightly annoying
<daveshah>
That method is mostly used for the GUI, arch checks etc
<daveshah>
It doesn't need to be very fast but it should be complete
<omnitechnomancer>
What does the check actually do with it btw?
<omnitechnomancer>
ah it checks that the names are reflexive
<omnitechnomancer>
and that bound nets actually contain wires?
<daveshah>
Yeah
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* mwk
reads "infertile wires" instead of "intertile wires" and wonders just wtf is going on
<mwk>
also, morning
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<omnitechnomancer>
morning mwk
<omnitechnomancer>
clearly the wires near the edge are infertile as they have no drivers :P
<____>
I bet fertility index is somehow connected to effectiveness factor. I just feel the correlation..
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<omnitechnomancer>
Indeed, atleast the anlogic part is only 1.2k luts off its rounded size
<omnitechnomancer>
and about half of those are LUT5s so has atleast some vague claim to fudge factors
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<daveshah>
I think the CrossLink nx fudge factor is due to the hard IP
<daveshah>
In which case we could be calling all Zynqs million logic cell FPGAs
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<eddyb>
M E G A c e l l
<omnitechnomancer>
Yea
<omnitechnomancer>
daveshah: what do you think of the idea of have a separate "type" of wires for intertile routing wires and just placing those in every tile, including in "phantom" tiles outside the fabric so that all pips are valid?
<daveshah>
Yes, that makes sense
<omnitechnomancer>
Alternately could those pips check the wire location and just dynamically not show up when the wire lies outside the fabric
<daveshah>
I guess either works, the latter would result in a closer match between nextpnr arch and reality
<omnitechnomancer>
Well I have suspicion that some of those pips actually do go somewhere its just not where they go for the rest of the tiles, which causes annoying edge cases and will require a bunch of fuzzing to determine what exactly happens
<mwk>
the common thing is that the wires that would go out of range instead bounce back and become the wires that would go out of range, but with the other direction
<mwk>
ie. a wire that would be "sinkless" (or "undersinked") is matched with a "driverless" wire
<omnitechnomancer>
indeed
<omnitechnomancer>
so you get a bunch of extra routing between the edge tiles yes?
<mwk>
something like that, yes
<omnitechnomancer>
What usually happens with 1span wires in that case?
<mwk>
same thing
<mwk>
outgoing 1span bounced back to become incoming 1span
<omnitechnomancer>
do they just connect back to the same tile then?
<mwk>
yes
<omnitechnomancer>
for now I think I will try to add all the routing relatively and ignore ones that would come from outside the fabric, since that will just reduce routing choices
<omnitechnomancer>
but not be wrong
<omnitechnomancer>
I possibly still want a distinction between "inter tile" wires and other wires though
<omnitechnomancer>
daveshah: how important is the uphill and downhill stuff on the wires and arcs and so on? I suppose that is used to satisfy the various queries about such things
<daveshah>
Very important
<daveshah>
It's how the router traverses the routing graph
<omnitechnomancer>
cool
<omnitechnomancer>
I think I actually want most of the dedupchipdb stuff from trellis but just construct it more carefully
<azonenberg>
Anybody here using scopehal or glscopeclient for actual work yet? If not, have you tried? or are there specific blocking features/missing drivers?
<azonenberg>
LeCroy support is well developed, there's basic read-only support for R&S scopes
<azonenberg>
basic read-only support for Rigol DS1000Z but i have a guy working on a full driver for it now, no PR yet
<azonenberg>
and then lain/monochroma are starting to work on support for their Agilent, can't recall the series off the top of my head
<azonenberg>
but that may work with newer Keysight scopes, at least for basic features
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<miek>
i did some work on an agilent 5/6/7000 series driver a little while back, just haven't had time recently to finish it off
<azonenberg>
Awesome. lain, what was the exact model you had? (when you get up)
<azonenberg>
Maybe they can build off your code
<omnitechnomancer>
Hooray now you can observe all the PHY errata workarounds being applied
<azonenberg>
omnitechnomancer: lol
<mithro>
azonenberg: have you used Halscope with something like litescope?
<azonenberg>
litescope? what's that
<azonenberg>
and glscopeclient is the UI application, libscopehal is the driver layer, libscopeprotocols is the decoder/protocol analysis suite
<azonenberg>
support for the vivado ILA / chipscope core is on the wishlist
<azonenberg>
other ILAs certainly could be added
<azonenberg>
Eventual goal is to be able to synchronize an external DSO to a clock used in the design
<azonenberg>
to get fully synchronous capture with cross-triggering between ILA and analog
<omnitechnomancer>
It is quite astounding some of the PHY errata that exists
<mithro>
azonenberg: litescope support would probably get you _florent_ and gregdavill as users
* azonenberg
adds ticket
<azonenberg>
What's the host side interface to litescope, jtag? uart?
<mithro>
Etherbone
<azonenberg>
oh so it's socket based?
<azonenberg>
Even better
<mithro>
With adapter's for PCIe, UART, JTAG, USB, etc
<azonenberg>
But the same protocol on top of these various transports?
<azonenberg>
I can probably do the same thing i do now for SCPI where i have the LA class take in a WishboneTransport object and then that can be a JtagWishboneTransport et al
<mithro>
Talking to your ILA via GigE is pretty magical :-)
<azonenberg>
Yeah as long as you're using florent's ethernet IP i guess
<omnitechnomancer>
just done venture towards 10G SFP Ethernet, especially copper, that way has many cursed corners
<omnitechnomancer>
dont*
<azonenberg>
omnitechnomancer: actually 10Gbase-R is quite simple and clean to work with
<azonenberg>
10Gbase-T, on the other hand, run for the hills
<azonenberg>
I have a bunch of 10G and 40G NICs, 10G switch with 40G uplinks and 40G capable FPGA devkit
<azonenberg>
but i've only actually done 10G with it so far, i have yet to try bringing up a 40G link
<azonenberg>
(the 40G uplinks are disused right now as i haven't pulled any MPO fibers from the switch rack to my desk yet, i just have a single duplex LC)
<omnitechnomancer>
Depends if the PHY between your MAC and your SFP+ was manufactured by a corporation beginning with M
<azonenberg>
what phy?
<azonenberg>
my 10G stuff was using a xilinx fpga with native 10G capable serdes
<azonenberg>
so i just did the 64/66b in gateware and spat raw ethernet frames out the GTX
<azonenberg>
i only use dumb passive poe so the biggest holdup will probably be getting some proper .af gear i can probe
<azonenberg>
Speaking of which...
<azonenberg>
I want to make a shirt with a schematic of a PoE transformer on it
<azonenberg>
and the caption "I'm 802.3 AF" :p
<omnitechnomancer>
though the negotiation is that the device has a resistance, or LLDP
<omnitechnomancer>
well, that it presents a specific load at various points during power up to signal which class it is
<azonenberg>
yeah but that should be possible to measure right?
<omnitechnomancer>
should be able to if you are watching the right lines I suppose?
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<omnitechnomancer>
pretty much the PSE presents varius common mode voltages on the pairs it will supply power on and the PD is expected to do various things to declar what class it is, including AFAIK nothing and then use LLDP to negotiate power after initial power up
<azonenberg>
Yeah
<azonenberg>
i havent looked into the nitty gritty of "proper" poe much
<azonenberg>
all of my cameras etc just run on... 48v i think? common mode voltage with no brains whatsoever
<omnitechnomancer>
I believe the class negotiation basically involves placeing a resistor across the power input so that it draws the right current during classification
<omnitechnomancer>
I think you can make a PD that will work with both
<omnitechnomancer>
though I believe a standard compliant PD must accept power on either set of pairs
<azonenberg>
Correct
<omnitechnomancer>
not all of them do since transformers cost money
<omnitechnomancer>
well not all PDs do, those which dont are not standards compliant
<omnitechnomancer>
and bt allows more power by using higher currents and all 4 pairs
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<eddyb>
just looked at the distrelec.ro order (for the couple digilent pmods) and it started in Eindhoven, NL..... so they just have a translated website and the stock wasn't local or anything :/
<eddyb>
this is what I get for not paying attention (but I'll get them by tuesday I guess)
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<q3k>
currently bisection yosys, hoping someone maybe filed a bug for this?
<q3k>
(i might have at some point in the past? i don't remember)
<q3k>
(oh. bram on ice40, forgot to mention)
<tnt>
q3k: well, if you have an async read port, you're kind of hoping yosys will somehow manage to move the register at some point ...
<tnt>
which really if wishful thinking and not exactly surprising that it breaks randomly.
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<q3k>
that's what migen gives me when i ask for a syncfifo
<q3k>
maybe i should try bumping migen
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<tnt>
err, that's not good. IMHO a good fifo design has (1) the output be directly the sync bram output or a register, no comb logic whatsoever after it. (2) full/empty flag should also be direct register outputs. (3) wren/rden should have minimal comb logic before the next register, 1 LUT layer is ideal.
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<juri_>
q3k: o/
<tnt>
lain: Oh, I have a 3000x so if you write a driver, I'm looking fwd to testing :P
<lain>
:3
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<adamgreig>
lain: have you started on the keysight driver at all? I've been meaning to have a go at at least basic acquisition for my 3000x but haven't done anything yet...
<anticw>
omnitechnomancer: anlogic parts are lut5 or a mix of 4 and 5?
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<lain>
adamgreig: haven't started yet, no
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<ZirconiumX>
I should ramble more about the CV, given I seem to be one of the few interested in it
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<GenTooMan>
CV?
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<ZirconiumX>
Cyclone V
<ZirconiumX>
Which got die-shrunk with extra RAM into the Cyclone 10GX
<ZirconiumX>
GenTooMan: ^
<ZirconiumX>
Abbreviations for this stuff are hard; if I pick a Xilinx-style "first bit of the part code", I end up with "5C"/"EP5C" which definitely won't get confused with the ECP5
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<GenTooMan>
What Cyc5 doesn't work?
<ZirconiumX>
Then you have weird things like "Str5" :P
<GenTooMan>
Well anyhow I'm surprised anyone is using Intel parts for anything. Altera use to be easy to find things on their website. Now you have to use google and go through the back door. So what do you want to use a Cyclone 5 for?
<GenTooMan>
Hey weird is memorable ... sometimes it's hard to remember things otherwise.
<ZirconiumX>
I actually originally bought a CV dev board for the MiSTer
<ZirconiumX>
Thought it might be neat to get MiSTer cores under FOSS synthesis
<ZirconiumX>
(the answer is that the MiSTer community was not nearly as friendly as the FOSSi community is)
<TD-Linux>
that and MiSTer cores tend to be hard to rebuild / a mix of VHDL and verilog
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<ZirconiumX>
Indeed, but I remain hopeful :P
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<ZirconiumX>
That being said, I have become increasingly convinced that trying to use Yosys as a synthesis frontend to Quartus is a path fraught with peril and Quartus bugs