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<anticw> gregdavill: qfn72 variant has one mipi port with 1 or 2 lanes?
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<m_w> gregdavill, what was the magic to get the DDR litex test with trellis?
<gregdavill> I'm still digesting the docs. From what I can tell it has one D-PHY with 4 lanes broken out. So 1x CLK, 4x DATA.
<gregdavill> m_w: The magic for me was updating my prjtrellis libraries.
<m_w> hmmm
<gregdavill> And also when switching between the DDR test (wishbone bridge) and the DDR SoC I had to change 1 line in my ecp5ddrphy. I've commented the line on my repo.
<gregdavill> ecp5ddrphy.py line 443
<gregdavill> What issues are you having getting it working specifically? synthesis problems? or runtime problems once the bitstream is loaded?
<m_w> let me run the compile again with the updates trellis installed
<m_w> looks like routing failed this time
<anticw> gregdavill: thx, i never understood why fpga vendors don't just put a pinout table in the datasheet ... vs some .xls thang i don't want
<anticw> daveshah: how can you tell the sram is double pumped?
<gregdavill> anticw: I get that, but also I don't want to hand transcode pins from a datasheet (esp. for a 400 pin BGA...) into a schematic symbol, a csv/xls file I can machine process.
<gregdavill> m_w: You'll need to update: trellis, nextpnr_ecp5, yosys.
<m_w> okay on it
<TD-Linux> anticw, it explicitly says so in the memory reference doc
<m_w> what does it mean when it was it cant import database again?
<m_w> *it says
<m_w> nevermind the path