##openfpga on 2020-01-16 — irc logs at freenode.irclog.whitequark.org

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04:38 <bluezinc> azonenberg: yeah, was totally in this channel...

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10:23 <edbordin67> woops, left my client connected on another machine :P

10:27 <edbordin67> I've been doing a little bit of prodding in Anlogic's IDE and I triggered an assertion error that referred to "hierdb". I am now looking at some obscure Mentor document talking about converting a ".hierdb" file into a "TCL model"

10:27 <edbordin67> (by "prodding" I am strictly talking about fuzzing files)

10:29 <edbordin67> Does hierdb ring any bells for anyone? I read some comment somewhere (I have now forgotten) that said they licensed most of their tooling from some other company so I am thinking there's a good chance I can get hold of someone else's tools to easily decode these files

10:31 <edbordin67> (specifically I am referring to this https://s3.amazonaws.com/public.verification.academy/app-notes/Application_Note_CDC_FPGA_v6.2.pdf )

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12:48 <gruetzkopf> https://gruetzkopf.org/openfpga/Bildschirmfoto%20zu%202018-09-03_14-21-24.png i just noticed that i should have known about usb4 details in september of 2018

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18:55 <stefanct> is there an easy way to override certain properties defined in fusesoc .core files from the command line?

18:55 <stefanct> (and is there a more suitable channel to ask this questions than this one?)

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20:31 <Finde> stefanct: you may want to try https://gitter.im/librecores/fusesoc

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