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<GenTooMan> It's hard to guess how many samples they made it depends on the process mostly generally engineering samples are the step before production so if using 8" the wafer scale package is 3.7x4.1 wafers 2100 die per wafer with a yield between 50 and 70 so hmm roughly 1300? I can see that happening, especially for what those things are, their is a big market for something like that.
<azonenberg> GenTooMan: 50-70% yield sounds very low for small dies on a mass prod process
<azonenberg> i'd expect 80% or more
<azonenberg> probably 90s
<azonenberg> Also, you don't know how many wafers they made. And don't forget to allow for scribe lines between dies
<azonenberg> with small CSPs the width of the saw lines is a significant contributor to overall area :p
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<rombik_su> TSMC advertising >95% yield on 28nm nodes, but we don't know about any silicon errors. :3
<azonenberg> You can't put a single yield on a process
<azonenberg> It depends on a lot of things, like how much of each layer is using minimum feature sizes etc
<azonenberg> how big your dies are is a big thing too, because defects are per unit area
<azonenberg> the bigger your die is, the higher the probability of a random defect being on one
<azonenberg> and the more silicon is wasted due to a single point defect
<rombik_su> Absolutely, it was estimated for mid-range dual-core SoC project (can't remember the die size), so I guess it will be even better for smaller die.
<azonenberg> Yeah. With a ~15mm^2 die i'd expect yield at probably 98% or better
<azonenberg> on a mature process
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<GenTooMan> azonenberg I hope you have considered that engineering samples are what’s left over of the first article batch in that thinking.
<azonenberg> GenTooMan: yes, but fabs dont normally fine tune the process for each customer's wafers
<azonenberg> unless you're an early adopter, your ES should have the same yield as your production
<azonenberg> just might have some silicon errata
<GenTooMan> It's unlikely they would use the full first release as engineering samples. :D
<GenTooMan> That's really all I was thinking, it's hard to know anything more honestly. Well I wish you a good night, I am up too late.
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<omnitechnomancer> ZirconiumX: Yes you can use luts for add/sub but who knows why there is an invert on one input of the sum unit then, that could be done in LUTs too surely?
<azonenberg> GenTooMan: the way it normally goes is, you order N wafers for the first batch
<azonenberg> package a handful of them (untested) for initial testing and bringup work
<azonenberg> once you're confident there's no fatal flaws, you write a factory test program, test and package the rest of those chips, then ship them off to customers as engineering samples
<azonenberg> if you're lucky, that same mask set is used for mass prod
<azonenberg> if early adopters / your in house testing finds bugs, you respin
<azonenberg> maybe repeat the process sending out ES2 silicon
<azonenberg> then once ready for prime time, you go to production
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<daveshah> From another DigiKey message (the one Greg posted on Discord), production silicon is expected Q1
<daveshah> So can't be too much wrong with the ES
<daveshah> that ties in with the eval boards being available 25th Feb too
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<rombik_su> daveshah: There's a Discord channel for open FPGA stuff?
<daveshah> Yeah, esdens 1bitsquared one
<rombik_su> daveshah: Thanks!
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<omnitechnomancer> What is the default state for a TTL UART line? low?
<gruetzkopf> high
<omnitechnomancer> does a constant low read as anything?
<rombik_su> High-to-low transition is the start bit; low-to-high is the stop bit
<rombik_su> You can't read anything unless there's a transition
<omnitechnomancer> ah okay, so a constant low is not exactly a valid condition but should not produce any output?
<rombik_su> In 99.9% cases UART peripheral won't be able to receive it as a byte (no rx event would be generated if it's makes sense).
<gruetzkopf> if your receiver detects that that's the BREAK condition (low for longer than one character time), but it should not produce output
<omnitechnomancer> ah
<gruetzkopf> (which i've only ever needed to transmit for breaking back into openfirmware on old sun machines)
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<ZipCPU> A constant low is known as a "BREAK" condition
<ZipCPU> Ahh ... now I see that gruetzkopf got that.
<ZipCPU> My first serial ports were full featured, and as feature complete as I could make them. BREAK conditions were part of that support, as were 5-bit, 6-bit, 7-bit, and 8-bit characters, even, odd, mark, space, and no parity, and two stop bits. Then after using the core for a year or so, I realized I never used any of the other features.
<swetland> yeah the world basically settled on 8N1 long ago. sometimes hardware handshaking.
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<azonenberg> swetland: yeah my uart ip is 8n1 only
<swetland> baudrate is pretty much the only tunable I bother including for uarts
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<GenTooMan> for bit rate generation it's possible to make fractional generators for a wider range. It's uncertain however that will be ever used. It is amazing that UARTs have been around for more than or almost 70 years.
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<TD-Linux> break condition is mainly used on rs-485 and dmx512
<gruetzkopf> these days, sure. on old sparcstations, break on console was equivalent to <stop>-a on the keyboard and dropped you into the openfirmware prompt (which is usable as a machine monitor)
<swetland> I usually do 1-3mbps -- usually easier to generate than 115200, well supported by ftdi usb/serial adpaters, etc
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<TD-Linux> oh wait also I think on dmx512/rs-485 it's not actually break, but a delay with the signal *not* asserted (high)
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* pie_[bnc] wonders how much it takes to make a CAD with a business case...
<shapr> I kinda miss openfirmware
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<gruetzkopf> has anyone here built *sd*-sdi output support yet? i have stupid plans and old hardware
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<mithro> gruetzkopf: poke felix_ maybe?
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<felix_> gruetzkopf: nope, i'm only working on hd/3g/6g sdi
<felix_> ok, tbh the project is a bit stalled at the moment, but it's still on my todo list and from time to time i do get around to continue to work on it a bit
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<felix_> oh and if you want to implement sd sdi, i'd highly recommend not to try to find the smpte specs, but use the itu recommendations
<felix_> the itu stuff is much more useful and contains information the official spec somoehow lacks...
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<ZirconiumX> You know, it never ceases to surprise me how well the ECP5 keeps up with the Cyclone V.
<ZirconiumX> Despite the CV being LUT6 to the ECP5's LUT4