<ZirconiumX>
I was kinda inspired by the logic here
mkru has quit [Quit: Leaving]
Thorn has quit [Ping timeout: 260 seconds]
Thorn has joined ##openfpga
Cerpin has joined ##openfpga
genii has joined ##openfpga
<indy>
hi all, doesn ecp5 has serdes support (for pcie)?
<daveshah>
Yosys and nextpnr support the serdes primitive
<daveshah>
There isn't an open source equivalent to the Diamond serdes wizard though, so you would pretty much have to copy and paste the magic values from that
<indy>
which magic values?
<daveshah>
There are various undocumented equalisation, CDR and PLL settingw
m4ssi has quit [Remote host closed the connection]
Xark has quit [Ping timeout: 268 seconds]
Xark has joined ##openfpga
Sinclair2 has quit [Quit: Bye Bye]
rohitksingh has quit [Ping timeout: 260 seconds]
X-Scale has joined ##openfpga
rohitksingh has joined ##openfpga
<azonenberg>
daveshah: i started something like this for 7 series GTPs a while ago that was a parameterized verilog IP core that took an argument for the standard and would drop in a bunch of presets
<azonenberg>
no code gen needed
<azonenberg>
but havent touched anything on ecp5 serdes yet
mumptai has joined ##openfpga
rohitksingh has quit [Remote host closed the connection]
Bird|otherbox has quit [Ping timeout: 260 seconds]
Bird|otherbox has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 255 seconds]
etrig has joined ##openfpga
genii has quit [Quit: Morning comes early.... GO LEAFS GO!]