ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
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<cr1901_modern>
https://youtu.be/Sz7ymNZ4cuA?t=2569 Also, Unreal Superhero 3 sounds _surprisingly_ accurate on the Genesis. Is it "just" using the PSG a lot?
<cr1901_modern>
Maybe someone ported the Genesis Toy Story MOD player to Sonic as a joke...
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<fseidel>
cr1901_modern: I just went through the instruments for UE3 and it's just a sawtooth for the bass, a few drum samples, and distorted pulse waves of various duty cycles
<fseidel>
the intro sounds like the PSG, rest sounds like close but not 100% exact FM reproductions of the instruments
<fseidel>
the bassline is probably the farthest off of any of the patches
<fseidel>
also, cool, exposing that card could make for great VGM playback :D
<fseidel>
I actually watned to do something similar with OPL3 a few years ago when I took an OS class. The reference box had a SB16 in it and I wanted to add a syscall to map the registers into userland for VGM playback :D
<fseidel>
never got around to it though, seeing as I was busy doing the actual assignments
<andlabs>
UE3?
<fseidel>
*US3
<fseidel>
Unreal Superhero 3
<fseidel>
I can't type today
<fseidel>
(or ever)
<andlabs>
what is that
<andlabs>
also to answer cr1901_modern's question in mastodon
<andlabs>
which is apparently super complicated, and does not use the code I linked above
<fseidel>
looks like most of the code here is just driver boilerplate
<fseidel>
there's very little actually driving the OPM
<andlabs>
where do these devices get created...
<fseidel>
that KC/KF table seems off to me, keeping an 4MHz OPM tuned as if it were a 3.58MHz OPM requires a KF of 5
<fseidel>
(assuming I did my math right, you also have to subtract 2 from the note, and wrap the octave down if needed)
<andlabs>
I don't remember what the OPM in the x68k runs at
<fseidel>
4MHz
<andlabs>
huh
<andlabs>
okay looking at the first file i linked again
<andlabs>
yes, the OPM is literally only used for the bell
<fseidel>
lol
<andlabs>
most of that code does not exist if you disable that feature at compile time
<andlabs>
the OPM timer is used for ADPCM timing somehow????? but other than that
<fseidel>
that's really odd to me, I was under the impression that ADPCM on the X68K was basically just done by hooking up the ADPCM decoder to a DMA channel
<fseidel>
I wonder what the heck the timer is doing
<andlabs>
also fdc_force_ready()
<andlabs>
whatever that means
<fseidel>
fdc -> floppy disk controller
<fseidel>
man, that's _really_ odd
<fseidel>
I don't recall the FDC having anything wired up to the 2151, but let me check the schematic
<andlabs>
...the register it writes to is 1b
<andlabs>
which is ... LFO waveform and CT bit
<andlabs>
#defineOPM1B_CT1MSK(0x80)
<andlabs>
#defineOPM1B_CT2MSK(0x40)
<andlabs>
CT bits
<andlabs>
those are what's being used
<andlabs>
so what are they
<fseidel>
CT appears to be 2 bits that map directly to 2 IO pins
<andlabs>
the former is used for ADPCM and the latter for FDC
<fseidel>
It seems they decided to use the YM2151's IO pins to handle device enable on those devices...
<fseidel>
guess I can't blame them, they're all on the I/O board, and the pins were there
<fseidel>
it's just odd.
<andlabs>
yeah
<andlabs>
those two bits ar ewired directly to those pins
<andlabs>
Now I Know™
<cr1901_modern>
>it appears NetBSD uses the OPM chip to provide the terminal bell
<cr1901_modern>
Okay, that's hilarious
<cr1901_modern>
4MHz is a fairly common frequency to run OPM at, even if the manual recommends colorburst
<andlabs>
control-g to your heart's content~
<cr1901_modern>
I also suspect that on the oldest x68ks, it's not even 50% duty cycle 4MHz
<andlabs>
who needs colorburst when you have a proper monitor and you aren't limited to NTS
<andlabs>
C
<cr1901_modern>
(which is legal according to the datasheet)
<cr1901_modern>
dunno how common on-die PLLs were back then
<andlabs>
not sure what non-50% duty clocks would accomplish
<cr1901_modern>
That's the guy who killed Mozart right?
<cr1901_modern>
(Joke)
<fseidel>
lol
<cr1901_modern>
Which I guess raises another question... how did future x68ks generate the 4MHz clock, and was it 50% duty cycle?
<fseidel>
I have an XVI and a logic analyzer, and will be on vacation starting tuesday... :D
<fseidel>
sounds like I should take a look into this
<cr1901_modern>
I would be _very_ interested in this info if you can set aside time to do it
<fseidel>
my money is on "no, it's not 50%"
<fseidel>
I need to open the thing anyway to install a battery holder, may as well probe ASA while I've got the sides off
<cr1901_modern>
2151 datasheet says it needs to be above... actually it doesn't give a percentage. Somewhere in the logs, wq calculated it to be 40% cycle at 4MHz, and the timing gets less strict at lower freqs.
<cr1901_modern>
And I've def run it like that from a Spartan3 FPGA when I couldn't be arsed to use the DCM
<cr1901_modern>
to generate 4MHz from 50
<cr1901_modern>
fseidel: Well, I would appreciate that info, but don't go through too much trouble to get it. Mind if I poke you about it on Fri?
<fseidel>
no problem
<fseidel>
I'd love to find out
<fseidel>
although looking at the schematic, I think I already have an answer
<cr1901_modern>
Oh?
<fseidel>
there's a 40MHz crystal
<fseidel>
as well as a 33.3MHz one
<cr1901_modern>
lemme guess
<fseidel>
40 -> 4 is pretty trivial, so I think that's where our 4MHz comes from
<cr1901_modern>
33.3 goes to the CPU
<cr1901_modern>
40 goes to everything else
<fseidel>
CPU gets 16, not sure how they derive that one
<cr1901_modern>
Well, that's something you could probe :P
<cr1901_modern>
Would be interested in that info too
<fseidel>
it looks like they take in 30 and 33.3, then output 10, 20, and 10/16(this one is selected from the switch on top)
<fseidel>
not sure how I'd probe that, it's all happening inside the IC
<cr1901_modern>
ahh I thought the 16MHz clock line would be output on a pin
<fseidel>
if you take a look at the second schematic I sent, the CPU clock is "MPUCLK" on the bottom right of ASA
<fseidel>
pin 129
<cr1901_modern>
Ahh the schematics weren't working for me (this is _my_ fault, not the server's)
<cr1901_modern>
I'll take a look in the morning
<fseidel>
anyway, not sure there's actually anything for me to scope then, given that there's a 40MHz XTAL right there
<cr1901_modern>
Understood, but thanks for offering. I _do_ appreciate it :).
<fseidel>
no problem :-)
<cr1901_modern>
Dunno if you can tell, I don't know much about x68k :). Just bits and pieces wrt how the ym2151 is interfaced.
<cr1901_modern>
B/c I subconciously wish OPM/N had more love on PC platforms and I'll never be able to afford an x68k
<fseidel>
yeah, these days, the only way to get one is to buy it dead and pray it's fixable
<cr1901_modern>
I'll buy a Quadro (a?) when I am in a position to enter 68k world
<fseidel>
I lucked out and got one that only needed recapping and some minor trace repair to patch where the cap fluid ate through, but some of these can apparently be pretty nasty
<fseidel>
(quarternary salt caps, they're extra bad)
<fseidel>
what I'm hearing is "the Quadro needs an OPM card"
<cr1901_modern>
I mean, that's also possible :P. Though a long ways off for me personally
<cr1901_modern>
Anyways I'm using Quadra (oops) as an example b/c it's the cheapest way I've found to actually get a 68k machine. Low end laptop is... $50 on Ebay?
<fseidel>
4MHz clock comes from IC20, which seems to come from magical 16MHz clock block X1
<fseidel>
I'm not getting any results for the part number CR580047CE, and my girlfriend can't make out the blurry kanji, so I'm at a dead end on this one :/
<fseidel>
with a bit of "google translate bruteforce" to figue out what the kanji might be, it appears that X1 is "hasshinki"
<fseidel>
so it's literally just a 16MHz oscillator
<fseidel>
mystery solved.
<cr1901_modern>
oh... oops
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<nukeykt>
Can anyone who can edit this page correct info about ym2413 test mode? It is identical to vrc7
<Lord_Nightmare>
so the test reg is exactly the same as vrc7?
<Lord_Nightmare>
does the 'dac test' thing with address 0x10 work the same on vrc7 as it does on ym2413?
<nukeykt>
Apparently it is not really dac test mode, it uses test bits 0 and 2. When test bit 2 is enabled phase generator will reset on each iteration and will output increment value which could be controlled used 0x10 register, bit 0 forces eg output to zero attenuation
<Lord_Nightmare>
nukeykt: "If bit 0 is set, this can be combined with setting bit 2, and writing the 'desired' dac value to register 0x10. Bit 2 will reset the phase generator every tick, which combined with 0x10 to set the frequency LSB, can be used to crudely force the dac to a specific value as the phase generator will increment within the sine wave to that position and become 'stuck' there"
<Lord_Nightmare>
"this isn't exactly a dac test, but does allow choosing a specific value within the sine wave to be forced to the dac" ?
<Lord_Nightmare>
does that seem right?
<Lord_Nightmare>
I'm assuming that's right.
<nukeykt>
You also need to write 0xFF to 0x20 and to 0x30
<nukeykt>
In this mode it still does FM though, so modulator has some impact
<Lord_Nightmare>
got it. I'll add a note about that.
<Lord_Nightmare>
note added
<Lord_Nightmare>
nukeykt: anything else? should I add the ROM stuff you worked out from the ym2413 to that page?
<nukeykt>
yeah, that would be nice. I think it is very close to actual values
<nukeykt>
looks like this info is missing: test bit 1 sets each bit of rhythm noise LFSR value to 1
<Lord_Nightmare>
ah, let me add that
<Lord_Nightmare>
so test1 also resets the lfsr
<Lord_Nightmare>
added
<nukeykt>
cool, thanks
<Lord_Nightmare>
I'll add the ROM stuff later, I need to finish some other stuff first
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