<gruetzkopf>
"Cable length targets and limitations are intentionally not imposed by this specification."
<gruetzkopf>
"hase jitter impact from the reference clock increases with longer cable delays, thus decreases
<gruetzkopf>
the PCI Express electrical budgets available to Link. Budget allocation, as provided within this
<gruetzkopf>
signaling and 24 AWG wire. Any attempt to obtain a larger round-trip delay (longer cables)
<gruetzkopf>
to the longest cable that can be achieved, from an insertion loss perspective, using PCI Express
<gruetzkopf>
cable specification, has chosen a maximum round-trip delay of 70 ns. This is roughly equivalent
<gruetzkopf>
requires jitter budget tradeoffs to be made or an alternate clocking architecture."
<awygle>
that's, uh... 45 feet.
<awygle>
big cable.
<sorear>
round trip tho
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<awygle>
Oh good point.
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<kc8apf>
I've used 10 foot iPass cables for PCIe in the past. It does work.
<awygle>
My dream of PCIe over bed of nails lives on
<whitequark>
hm
<sorear>
probably won't work with iron nails
<gruetzkopf>
if you can tune the dllp timout you can do more
<gruetzkopf>
iirc you can set the TLP timout to something awful like 2¹⁶-1ms
<gruetzkopf>
which is something like 6.58*10⁹m
<gruetzkopf>
(i hope you're not doing any reads when you do that though)
<whitequark>
awygle: re chips with "confidential" datasheets: my personal rule is that i'd use them if i don't expect vendor's support (which is my usual expectation anyway, vendors have been damn near useless historically)
<whitequark>
sure, they can disappear at any point, but... remember how the 12-bit ADC i used on glasgow effectively poofed?
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<Stormwind_mobile>
Are there any tricks obtaining NDA'd datasheets and other stuff? Do I need do be able to communicate in chinese on some obscure forum or how does one go about that?
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<whitequark>
a lot of it is in the open
<whitequark>
like, searching on pudn often gives excellent results
<awygle>
whitequark: yeah I never expect support, but I worry about life cycle. Although like you said, TI is no guarantee...
<whitequark>
awygle: life cycle, or availability?
<whitequark>
the TI part in question is Active but missing... meanwhile lots of parts discontinued 20 years ago are still fairly easily available
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<whitequark>
gruetzkopf: got the CC2531
<gruetzkopf>
oh, a ti part that still exists
<gruetzkopf>
great!
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<whitequark>
what do you mean? it's the one you asked me to get
<hell__>
gruetzkopf: w.r.t. external PCIe cables and such, you remind me that IBM has some expandable servers where you can bridge two of them with special cables. these cables carry three QPI (QuickPath Interconnect) links. O_o
<gruetzkopf>
hell__: i know
<gruetzkopf>
wq: mostly stupid joking
<gruetzkopf>
referencing the earlier disappearence of the ADC
<gruetzkopf>
hell__: i have some AMD opteron based blades which you can stack an expansion blade to using HT, and then stack up to 6 pcie expansion blades on top of that!
<hell__>
o_O
<gruetzkopf>
(limited by the largest power domain ibm bladecenters had)
<hell__>
if only blades weren't so proprietary
<Stormwind_mobile>
whitequark: do you know about the legal status of pudn.com and the like? I found a bunch of info regarding that cheapwatch SoC, MT(K)6260. Most info requires a user account, though. Do I need to be careful, I.e. setup fake email, use TOR or something?
<Stormwind_mobile>
And what is dssz?
<hl>
Stormwind_mobile: link?
<Stormwind_mobile>
@hl to what exactly?
<whitequark>
Stormwind_mobile: "gray"
<whitequark>
it's more or less piracy
<Stormwind_mobile>
Will I have to worry about police kicking in my door if I setup an account there an download data?
<hl>
uh, no
<Stormwind_mobile>
Sure? ^^
<hl>
How the effing hell would you?
<whitequark>
nah, no one cares about datasheets
<whitequark>
even if you pirate music or software from western publishers, for the most part they'll only try to go after you if you distribute it
<whitequark>
whereas in civilized countries like china, a devboard vendor may well just share their cracked copy of FPGA toolchain in their dropbox; it's pretty normalized
<Stormwind_mobile>
XD
<whitequark>
(I'm using "civilized" sincerely here, to be clear)
<Stormwind_mobile>
I'd like a fully featured ready-to-go SDK with the reference hardware design, please
<whitequark>
i mean, i've seen those shared too on pudn
<whitequark>
for some company's in-house Bluetooth SoC CPU
<whitequark>
in-house as in, they made the ISA too
<Stormwind_mobile>
There are about a dozen if those cheapwatches, and they are mostly the reference design with minor changes, as it seems
<Stormwind_mobile>
Speaking of cursed footprints: The SoC comes in a BGA199 package, with a 19*18 grid, that is about 70% populated
<Stormwind_mobile>
I'm impressed by the feature set, and this chip is from 2013, as it seems.
<whitequark>
with the center unpopulated?
<Stormwind_mobile>
No, arbitrary pattern. Looks similar to a QR code, or rather a 2D barcode
<whitequark>
huh
<whitequark>
are you sure it's arbitrary? is it maybe to make routing easier?
<whitequark>
"just enough depopulated balls to avoid ViP"
<whitequark>
grasping at straws here
<Stormwind_mobile>
I have no idea an zero experience routing BGAs. Maybe? There will be *some* kind of reasoning behind that...
<hl>
interesting, broadcom switch chip datasheets, but they're passworded
<whitequark>
Stormwind_mobile: that looks like 19*17 grid to me?
<whitequark>
(it's symmetric on both axes)
<Stormwind_mobile>
Right. Miscounted
<Stormwind_mobile>
What's the problem with ViPs? Does the via suck away the solder ball and thus weaken the solder joint, or making it unreliable?
<gruetzkopf>
hm, last time i saw mt6260 was in bunnies and xobs' fernvale project
<Stormwind_mobile>
Is that so?
<hell__>
Stormwind_mobile: in that link you sent, you can click on the document name and it just opens
<awygle>
Yes, exactly stormwind (re vip)
<Stormwind_mobile>
So adding more solder paste specifically to via'd BGA pads to compensate for the loss won't work?
<Stormwind_mobile>
hell__: that single PDF, yes. There are a fee other entries with documents, many chinese, and many other entries require a login.
<Stormwind_mobile>
There are even files for the hardware reference design
<Stormwind_mobile>
gruetzkopf: that's a great hint, though I fear that this project has gone the way of the dodo, as so many did. Actually, I remember having read bunnies blogpost quite some time ago
<Stormwind_mobile>
One of the people I would have loved meeting at 36C3, but didn't.
<awygle>
You can still end up with voids, reducing structural strength. The "correct" solution is to plug the vias with epoxy during manufacturing and plate copper over the tops, but this is expensive, so there are various backoffs from there
<awygle>
Oh voids are also bad for thermal transfer, in the case of thermal vias
<Stormwind_mobile>
Wouldn't it be easier pushing the electroplating of the vias to plug them instead? Copper is more expensive than epoxy, but if you can save yourself the additional step during manufacturing?
<Stormwind_mobile>
Well, I understand it's a thing to avoid as much as possible
<whitequark>
i don't think you can plate that much
<whitequark>
youcan plate a few microns
<whitequark>
a few dozen i guess
<Stormwind_mobile>
Is the process actually electroplating, I.e. applying a current, or is it ... uhmm... "currentless" (what's the correct term?)
<Stormwind_mobile>
In any case, there will be mass flow problems getting those vias completely plugged, I guess.
<whitequark>
electrless plating
<whitequark>
electroless is used for final coatings a lot
<whitequark>
E in ENIG
<Stormwind_mobile>
Ahh, right!
<Stormwind_mobile>
But is this the process to plate vias, castellated pads etc.?
<davidc__>
Stormwind_mobile: I know you can get solid copper filled vias (for a premium). They're used in power electronics. I don't know how they're filled though
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<whitequark>
huh, interesting
<Stormwind_mobile>
0.8mm BGAs are not exactly power electronics, but whatever works...
<awygle>
You can actually plate shut
<awygle>
But then you need to deal with many many ounces of copper on the outer layers
<awygle>
And likely a nonuniform layer
<awygle>
So it's not just the cost of the copper in the vias, it's copper everywhere on the outer layers, and there's still an extra processing step
<awygle>
But copper kicks epoxy's ass in thermal conductivity so it's still sometimes done for holy-shit high power electronics
<davidc__>
Or where you already have stupid-thick traces anyways for the current, and need to get that through the board
<davidc__>
(But sometimes you actually use soldered-in metal stoppers, or rivets in that case)