<furan->
Is there anything in the Glasgow implementation that is highly specific to the parts on the board? I was thinking of porting it to de0-nano
<tnt>
de0-nano would be missing the FX2 and also all the IO buffers.
<furan->
I think I can live without the buffers. Not sure what lives in the FX2 but maybe I could fit that in a NIOS core.
<furan->
Is it just for USB?
<furan->
(Will get more familiar with the project, just on a shuttle with some time to kill)
<gruetzkopf>
usb, bitstream swapping, io voltage setup
<furan->
Kk
<furan->
My whole project will be at FPGA io vcc (1.8v)
<furan->
How many bitstreams are there?
<furan->
Or is the idea that people can just keep writing more
<tnt>
bitstreams are generated on-the-fly depending on the config.
<furan->
Neat
<whitequark>
furan-: note that although glasgow is intended to be reusable, the only hardware supported upstream will be our own
<whitequark>
it is simply not viable to test every possible combination forever, so everyone else is on their own.
<electronic_eel>
furan-: I think it would be much easier to couple a FX2 breakout board with your de0-nano. I guess it'll still be enough work to get it running...
<furan->
Well I use a trick on Altera boards where my transport is actually just jtag I to the FPGA core
<furan->
And I reverse engineered their lowest level jtag dll. I get about 3.2 megabit a sec
<furan->
But yeah I was thinking of getting an fx2 breakout that’s a good idea
<furan->
Whitequark for sure that is totally expected
<furan->
I to = into
<electronic_eel>
3.2 mbit/s is about 2 orders of magnitude slower than glasgow with the fx2. I get 336 mbit/s with the loopback demo between the ice40 and the glasgow python app on the pc
<noopwafel>
my first attempt at a glasgow just went through the reflow oven