00:00 <whitequark> ... you know what i gotta take that thing apart

00:00 <whitequark> the more i think about it the more cursed it seems

00:00 <hl> i bet it is an effing router

00:00 <hl> reason: I once tried to find a VDSL2 PCIe card online, and was unable to do so, except for some really niche product which also stated it doubled as a router (WTF)

00:01 <gruetzkopf> it basically has to be

00:01 <hl> my conclusion: nobody is making VDSL2 client silicon that isn't also a router SoC

00:01 <gruetzkopf> not true

00:02 <hl> hm, really?

00:04 <gruetzkopf> even in my dsl router the DSL transceiver is a pcie device

00:05 <hl> huh

00:05 <gruetzkopf> (intel/lantiq anywan vrx518)

00:05 <gruetzkopf> (in a avm fritzbox 7590)

00:09 <gruetzkopf> (next to a anywan grx550 - which means that intel makes FAST (2.4GHz) dualcore mips

01:00 <XgF> hl: with VDSL(2) the connection is coming out as PPP(oE)

01:00 <XgF> hl: With ADSL it can be more cursed and instead pop out as PPPoA or PPPoEoA

01:00 <hl> yeah

01:01 <XgF> PPPoEoA presumably being designed to maximize overheads or something

01:08 <whitequark> it what

01:16 <XgF> PPP over Ethernet over ATM (Adaption Layer 5), rather than just running PPP over AAL5 directly

01:17 <XgF> So you both pay ATM framing overheads on your ADSL line, and also eat 8 bytes MTU due to PPPoE overheads

01:19 <XgF> I have no idea how or why ADSL was designed such that ATM nonsense can bleed through it

01:25 <XgF> I guess its probably from when the telecoms industry thought everything was going to be ATM, instead of Ethernet eating everything

09:24 <gruetzkopf> the ATM sublayer makes link bonding very easy

18:18 <zkms> i still dont know what ATM is and at this point i'm a bit afraid to ask

18:31 <awygle> zkms: https://en.wikipedia.org/wiki/Asynchronous_transfer_mode

19:01 <noobos> hi, sorry for the noob question. I probably missed something, but it seems that tx_rdy signal in the UART module is never going down.

19:02 <noobos> I see the code that sets it to 1 in IDLE, but I don't see any code that sets it to 0.

19:02 <noobos> what am I missing?

19:20 <Twix> https://m-labs.hk/migen/manual/fhdl.html#signal

19:21 <Twix> Signals default to 0. The signal is only in one state driven to 1. In all other states it defaults to 0.

19:23 <Twix> You may want to imagine it as an wire. In one state you connect it to a battery. In all other states it is unconnected.

19:27 <noobos> interesting. Is FSM state considered a conditional statement like If and Case?

19:29 <noobos> Also, I kinda have a code that uses the UART and transmits next char when uart.tx_rdy goes down. And it seems that it never does.

19:42 <noobos> My misstake. It transmits next char when uart.tx_rdy goes up again. Waits till it happens. The problem is, it never goes down and so, the code tries to transmit without waiting..

20:05 <whitequark> noobos: yes, an FSM state works like If and Case, with one important caveat: if you have x.eq(y) in a state, it works as if that was appended to m.comb, and if it's NextValue(x, y) then it works as if x.eq(y) was appended to m.sync

20:06 <whitequark> I suggest you try to simulate your design together with the UART, since it doesn't need to receive anything and just needs a clock

20:42 <noobos> whitequark thanks! I'll try to simulate it.