16:17 <d1b2> <DCC> Hi there.

16:22 <whitequark> hi!

16:28 <d1b2> <DCC> Who did the floppy dumping, dumping DCC may be roughly similar in terms of processing the distorted digital signal from magnetic storage.

16:30 <whitequark> i did

16:30 <whitequark> did we talk on twitter before?

18:01 <d1b2> <DCC> Don't think so, you just got mentioned in that thread afaik.

18:07 <d1b2> <DCC> Do you want to talk here, in glasgow-addons or privately about details, I have some questions?

18:10 <d1b2> <Attie> #glasgow-addons is discord only

18:10 <d1b2> <Attie> @DCC I'd just shoot some questions!

18:10 <whitequark> yeah i'm not actually in #glasgow-addons and i think i just learned about it?

18:10 <whitequark> anyways

18:11 <d1b2> <Attie> oh, sorry! I presumed esden would have said

18:11 <d1b2> <Attie> talking about physical addon boards, more than usage / development

18:12 <d1b2> <Attie> (e.g: PROM with ZIF... I'm looking at a CAN board, etc...)

18:13 <whitequark> why a separate channel anyways?

18:13 <whitequark> i think addons are very much on-topic here

18:13 <whitequark> since from day 1 glasgow was designed to take addons...

18:16 <d1b2> <Attie> not sure... I guess to keep on-topic / core dev, but if you're happy with that talk here (and not in #glasgow-addons), perhaps we should move over

18:16 <d1b2> <Attie> *and you're not in

18:18 <d1b2> <DCC> DCC tape is MP1 with some interesting additions (got documentation for that), rough data rate of 1 MBit/s. 9 tracks either parallel or multiplexed at 3,072 MHz with a clock and an indicator of the first track. Needs some kind of IIR and FIR according to documentation, never looked at it. I guess I have finally found the right tool for the job.

18:21 <d1b2> <DCC> Can you see edits on IRC or what you are on properly?

18:24 <whitequark> Attie: totally happy with it, would mildly prefer it even

18:24 <d1b2> <Attie> I'd guess not

18:24 <whitequark> i don't think this channel has enough volume to really warrant splitting it

18:24 <d1b2> <Attie> (edits)

18:24 <whitequark> no, i don't see edits

18:25 <whitequark> i'd like to have the current bridge replaced with matrix

18:25 <whitequark> i.e. matrix bridging plus matrix-discord bridging

18:25 <d1b2> <Attie> @wq, ok! I'll announce there

18:25 <whitequark> *that* actually works really well

18:25 <whitequark> but i don't want to ask 1b2 to put even more effort into what is surely an aggravating job

18:26 <whitequark> DCC: do you want the device to deserialize the data too, or just capture it?

18:26 <whitequark> is it analog or is it a pulse train?

18:29 <d1b2> <DCC> DCC tape is what is now considered MP1 with some interesting additions on metadata, a teletext like graphics format (ITTS) and more (got documentation for that), the raw data rate is roughly 1 MBit/s. 9 tracks either parallel or multiplexed at 3.072 MHz with a clock and an indicator of the first track. Needs some kind of IIR and FIR according to documentation, never looked at it. I guess I have finally found the right tool for the job. When I can

18:29 <d1b2> properly capture and decode it to bits I will have to think about the rest once I can get a closer look. It is binary + and - but needs some kind of filtering to make it work, can you see pictures via the bridge?

18:31 <whitequark> nope

18:31 <whitequark> (matrix has both editing and pictures...)

18:31 <d1b2> <DCC> I'll drop you a DM with it.

18:31 <d1b2> <DCC> From the service manual

18:31 <d1b2> <DCC> https://cdn.discordapp.com/attachments/613461005392936961/769266781738762270/unknown.png

18:31 <whitequark> ah wait this works

18:32 <whitequark> okay, so, how do you want to lay this out?

18:32 <whitequark> use an ADC plus glasgow and run DSP on the FPGA?

18:32 <whitequark> use analog filtering?

18:35 <d1b2> <DCC> Digital filters were used in the devices back then, I'll look at the details of the Glasgow a bit more. Thanks for the inspiration. When can I purchase a unit to Germany except for full DIY?

18:42 <whitequark> purchase: we don't have official production started yet, so your best bet is just asking here in this channel

18:42 <whitequark> twitter also works

18:43 <whitequark> filters: so far i've never did any DSP on the FPGA, but the performance of the (tiny) ice40 device might disappoint you, better evaluate some HDL before paying

18:44 <whitequark> personally i try to do DSP on the host machine with something like numpy

18:44 <whitequark> there's no reason you *can't* do a FIR or IIR filter on the FPGA, but it was spec'd as a protocol converter device, not compute device, so, again, better check that it fits your requirements

18:44 <tnt> Oh yeah, the HX lacks any multiplier.

18:45 <whitequark> and UP is so slow that the multipliers are kinda wasted on it...

18:46 <tnt> you haven't used the EOS-S3 yet ? :)

18:46 <whitequark> yes, it is incredibly funny that the previous slowest FPGA was called UltraPlus and the current slowest FPGA on market is called QuickLogic

18:47 <tnt> Ahaha, I hadn't even thought of that.

18:47 <tnt> But to come back on subject, unless you need to reduce the data rate to the host you're better off doing DSP in python.

18:48 <whitequark> and there is no reason to reduce the data rate here... glasgow can reliably transfer ~40 MB/s to the host which seems plenty for this use case

19:41 <d1b2> <daveshah> The internal codename for the UltraPlus is ThunderPlus which really isn't better

19:42 <Lofty> I have a slightly crazy idea regarding multiplication: you can convert to logarithms and add them

20:11 <d1b2> <TiltMeSenpai> hmm does that also work for division

20:11 <d1b2> <TiltMeSenpai> ice40's have dsp blocks with multipliers I think

20:21 <d1b2> <daveshah> only the Ultra/UltraPlus do

20:23 <d1b2> <TiltMeSenpai> oh lol

20:24 <d1b2> <daveshah> there were going to be 'HX+DSP' type iCE40s - the MS/MX series that would also have had HDMI and MIPI support

20:24 <d1b2> <daveshah> but they were canned after Lattice acquired SiliconBlue

20:25 <d1b2> <daveshah> the sim models for the HDMI and MIPI primitives among other things still lurk in the icecube and radiant data files

20:26 <d1b2> <daveshah> In the DSP user guide revision history, another reference lurks

20:26 <d1b2> <daveshah> > Added iCE40 UltraPlus and removed “MX series” to introductory paragraph

20:26 <d1b2> <daveshah> > Added iCE40 UltraPlus and removed “MS series” to introductory paragraph

21:09 <d1b2> <Attie> @DCC i'd be interested to read a bit about this - mind sharing the service manual?

21:10 <d1b2> <Attie> @DCC re purchasing, 1bitsquared / esden will be producing boards for the crowdsupply campaign - sign up here: https://www.crowdsupply.com/1bitsquared/glasgow

21:10 <d1b2> <Attie> @wq where does the signup link in README.md fit in? I'm probably on both lists a couple of times by now

21:17 <d1b2> <esden> Regarding CS campaign. The Glasgow revC2 prototype panels arrived. I will be switching over the PNP today to start assembling them. As soon as they are on the way to the core devs I can finalize the campaign stuff I think.

21:17 <d1b2> <esden> https://cdn.discordapp.com/attachments/613461005392936961/769308582918488074/IMG_2978.jpeg

21:20 <d1b2> <daveshah> Random production question, what are you planning to do about the headers? Solder-your-own like the icebreaker?

21:22 <d1b2> <esden> They will be all presoldered.

21:22 <d1b2> <esden> I mean, not all of them I think. but definitely the IO bank connectors, the Sync connector and the LVDS connector will be pre soldered.