hno changed the topic of #linux-sunxi to: /Allwinner/sunxi development discussion - Don't ask to ask. Just ask and wait! - See | | Logs at
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<wingrime> oliv3r: ping
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<oliv3r> wingrime pong
<oliv3r> if CIR is RC, then FIR and MIR are less ipmortant
<rm> well said
<rm> (:D)
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<Ehsand> hipboi_: hi
<Ehsand> hipboi_: /msg ?
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<mripard_> Turl: wingrime: devm_clk_get is a managed clk_get
<mripard_> that means that the clocks will be "garbage collected" when the driver is removed
<oliv3r> mripard_: dirty words!
<oliv3r> 'garbage collected', yuk :p
<mripard_> now, clk_get will either use of_clk_get or clk_get_sys to actually retrieve the reference to the clock you want
<FR^2> "say something dirty to me!" - "kitchen! bathroom! ..."
<mripard_> so yeah, bottom line is that you should devm_clk_get, except if you have a good reason not to.
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<FR^2> oliv3r: garbage first, mark-and-sweep or mark-and-compact?
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<oliv3r> :p
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<arokux1> hi
<oliv3r> lo
<mripard_> arokux1: hi :)
<oliv3r> mnemoc: patches! :)
<hno> I think we might need a patchwork.
<oliv3r> hopefully on the new server things like that would be nice
<mnemoc> ack
<hno> oliv3r, patch 3/3 have a poor subject. Unifying what?
<mnemoc> I got the new dedicated IP today
<oliv3r> Infrared
<utente> hi all
<oliv3r> hmm i don't see 1/3 yet on ML
<hno> I know, but git log --pretty=oneline don't..
<oliv3r> but yes, i need to write better commit messages :)
<hno> I see all three + cover letter.
<oliv3r> mnemoc: want me to resend or can you edit the file before merging (just append ' IR')
<utente> im using xchat, i can receive files but my peer cannto recdive mine. i dunbo if problem is me or him, can i send a t4est file to someone?
<hno> utente, you most likely are behind a NAT router that don't handle DCC.
<oliv3r> mnemoc: hansg wants to pull it into his branch, want to pull it from him?
<utente> hno... it could be. can i try to send a test pdf to you, hno?
<oliv3r> mnemoc: if i let hansg pull; i'll edit the commit message before pushing it
<utente> hno, can i?
<hno> utente, I am behind double NAT and doubt DCC work for me..
<utente> i can tra to sent? in worse case, it just fail.
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<oliv3r> mnemoc: i pushed it to github so you could pull from there
<hno> utente, you can try..
<oliv3r> or hansg; or both :)
<hno> oliv3r, yes that's the beauty of git.
<utente> hno, ok
<utente> no it fail.
<oliv3r> hno: i love git; when i started it was 'hard' to grasp the changes from svn, but i like it lots. just need to get better at it, ti's complexity makes it hard to master :)
<mnemoc> oliv3r: I'm setting up my desktop at work. I'll try to get into that soon
<oliv3r> mnemoc: no rush :)
<oliv3r> still don't see 1/3 on the ML :S
<oliv3r> stupid google groups
<mnemoc> hopefully i'll setup mailman soon too
<mnemoc> and leave the google groups thing for users
<oliv3r> :D
<oliv3r> mnemoc: you got an office and everything now? collegues too?
<hno> oliv3r, yes.. and svn is no fun at all when you have got used to git & bzr. But. need to learn git submodules better.
<oliv3r> i like how the sunxi-bsp is setup with the submodules
<mnemoc> oliv3r: yes, 7 people total... and a sock filtered coffee machine
<oliv3r> but yeah, i'm not all into it either
<oliv3r> mnemoc: coffee, yuk :p
<oliv3r> what OS is on the desktop?
<hno> mnemoc, maybe we should get a sysadmin for linux-sunxi?
<mnemoc> hno: you'll get your key there as soon as the lxc is installed and network configured
<mnemoc> this evening hopefully, now that I got the extra IP
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<oliv3r> if you need any help, just let us know :)
<mnemoc> i'm (slowly) getting things under control. but the (tested) pull branches are a GREAT help
<hno> gah... 3G networks.. randomly giving you a new IP without asking.
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<hno> mnemoc, good to hear that.
<oliv3r> hno: ack
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<hno> what was the last message you saw from me (before the 3G one)
<mnemoc> 11:39:07 < hno> mnemoc, maybe we should get a sysadmin for linux-sunxi?
<arokux1> I'm trying to understand what happens on major trees.. what about Hans de Goede, he is trying to assemble his own tree for fedora? i've got the feeling that his tree contains more patches than stage/sunxi-3.4
<hno> ok.
<hno> arokux1, he is reviewing and staging patches in general.
<arokux1> hno, what is the path for those patches to lend in kind of central linux-sunxi tree on github?
<hno> arokux1, there is no single path, but all path share the need for a review on linux-sunxi mailinglist.
<hno> and most times it's mnemoc that is the final gatekeeper for pushing into the linux-sunxi repo after review.
<hno> a process that is a lot easier if the one doing review first pushes to a personal repository, such as what hansg is doing.
<arokux1> hno, I see, thanks
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<_hipboi_> Ehsand, ping
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<_hipboi_> mnemoc!!
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<arokux1> _hipboi_, any news on cubietruck? :P
<oliv3r> alllready gone
<_hipboi_> arokux1, still preparing production
<_hipboi_> network is not good here
<oliv3r> :(
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<oliv3r> i don't see wingrime's cedarX unification in stage/sunxi-3.4 yet :(
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<woprr> re
<woprr> still no delivery from olimex UK but I've remembered ordering from another Britain with "Royal Mail (Small Packets)" a year before, could take 14 days to DE
<woprr> so I assume it's not airmail, cannot find the RM product "small packets"
<woprr> shipping cost the other seller noted is £0,99, too low for airmail
<FR^2> woprr: I ordered my cubieboard at - what did you order?
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<woprr> FR^2, olimex A20 micro
<oliv3r> woprr: are you german?
<woprr> yes
<oliv3r> why order from the UK then?
<oliv3r> olimex is a bulgarian company ;)
<oliv3r> i think if you order from their webshop, it should mail directly from bulgaria and arrive in a few days :)
<oliv3r> i got mine to NL deliverd in maybe less then a week?
<woprr> I know, checked the distributors list before, but thats +10 EUR and do they sell to consumers?
<woprr> well, VAT included, yes then
<woprr> +18 EUR DHL
<oliv3r> 18E for shipping?!
<FR^2> woprr: 18 EUR DHL?
<woprr> yes
<oliv3r> whole shit
<woprr> or trust bulgarian post airmail ;]
<FR^2> woprr: I ordered stuff for about 100 EUR and didn't have any shipping costs
<oliv3r> oh i would ;)
<woprr> > 100 EUR maybe shipping free
<FR^2> woprr: indeed ;)
<FR^2> woprr: "Kostenloser Versand ab 100€ innerhalb Deutschlands"
<FR^2> I ordered some power supplies, a breadboard for 3,20 EUR, the cubieboard2 and a case. That way I came above the 100 EUR. But if you don't have anything you could order that actually makes sense, ...
<FR^2> woprr: Wait a second... 3,50 EUR shipping costs via DHL
<woprr> yes. and?
<woprr> = olimex UK + ~10EUR
<FR^2> ah, okay.
<woprr> so I've got time to read in the manuals an start with dvb-soc.ko :)
<woprr> tuner hardware extension board later then
<oliv3r> woprr: dvb/sunxi.ko :p
<oliv3r> i'm very curious how you will handle that bit :)
<oliv3r> the tuner extension
<woprr> me too ;-)
<oliv3r> media/pci/sunxi/sunxi.ko ?
<oliv3r> while it's not connected to the pci bus
<oliv3r> ohh media/platform/sunxi
<woprr> dvb-sunxi is too specialized? can we not generalize to something like dvb-soc ?
<oliv3r> does dvb-soc exist? i see exynox, davinci, marvel all have their own driver
<woprr> there's no pci bus on allwinner boards
<oliv3r> no it's media/platform/sunxi/
<woprr> ok then it'll be namend dvb-sunxi.ko, thanks
<oliv3r> but what does it encompass (i know only a little about dvb framework)
<oliv3r> i know you have core, frontends, demodulators and tuners
<oliv3r> it's obviouisly not a tuner, but does it combined frontend and demodulator?
<oliv3r> or is it only frontend?
<woprr> dvb-core -> dvb-buffer-core > dvb-sunxi -> dvb-frontend
<woprr> depends videodev etc
<oliv3r> so it's a demod?
<oliv3r> (i don't know where to place the hardware and its functionality)
<woprr> CU1216 types receivers, tuner and demod included, ~30 manual processable pins direct to Ax0 TSx port
<oliv3r> CU1216 what?
<oliv3r> and more what?
<woprr> receiver module
<woprr> philips
<oliv3r> ah ok
<woprr> google picture
<oliv3r> ohh those old fashioned big cans
<oliv3r> i haven't seen the pin multiplex for it actually
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<woprr> no I've got the latest TDA10023 from QQBOX modules on ebay, silicon tuners are crap and not manual processable without lab or lead factory, too small mil pins, BGA etc
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<oliv3r> woprr: very true
<oliv3r> ok so tuner i know what that is
<oliv3r> then we have the demodulator, does the 'ts' do that bit?
<oliv3r> and usually you have a 'bridge' that connects the tuner and the demodulator to the PCI/USB bus
<oliv3r> that much I know
<woprr> for dvb-s 1 I've found 2 sharp receiver modules we've already got linux drivers for, but I will use the BSBSE1 from an old TT S2300, it has the better STV0299 demod, sharp older the STV0288
<oliv3r> so is the 'ts' unit only the bridge? or does it combined that (in a platform way)
<oliv3r> i actually have an old TT-1500 DVB-T card, i could 'borrow' that tuner :)
<woprr> those receiver modules come with the Ax0 compatible "dvb -interface" called in some tuner datasheets
<oliv3r> what is Ax0? I doubt they mean A10 and A20 :p
<woprr> can be direct attached to Ax0 TSx
<woprr> A10/20 :)
<woprr> A31 3 TS controllers? ;-)
<woprr> TSC
<oliv3r> TDA10046H is the tuner i have
<oliv3r> maybe i can repurpse it
<woprr> yes thats a dvb-t
<woprr> a very good
<woprr> but not dvb-T2 ?
<oliv3r> not sure, don't think so
<woprr> I would prefer the TDA10086 for dvb-s but not seen in any receiver module
<woprr> ...manually leadable ;)
<oliv3r> oh i even have a few dvb-s receiverss with tuners
<oliv3r> nokia dbox-1 and dbox-2 dvb-s
<oliv3r> and i have a dbox-1 dvb-c
<oliv3r> i smell harvestable tuners :)
<woprr> eheh ok, You've got it all!
<woprr> happy recycling
<oliv3r> yeah but don't know if i have time to actually build anything
<oliv3r> and b) don't know if i have the willpower to build as i have no use for it right now :p
<oliv3r> then again, connecting a tuner to the a20-olimex sounds like a fun project
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<oliv3r> do keep the info up on wiki ;)
<oliv3r> maybe i'll build it too :)
<woprr> dvb-c is easy to connect, dvb-s needs extra LNB/diseqc circuits and power supply
<oliv3r> ah yes
<oliv3r> dvb-t should be easy too
<woprr> where to put SMT connector dvb-receiver extensions modules in this wiki :?
<woprr> yes dvb-t too
<oliv3r> good question, just make a new page ;)
<woprr> makes no sense in my region only 12 state tv channels and you need a roof yagi
<oliv3r> trying to find the tda10046 pinout
<woprr> dvb-t transmitters > 50km away
<oliv3r> where is your region? i thought germany was pretty well dvb-t equipped
<woprr> you dont need the chips pinout, you only need the module pinout
<oliv3r> well yeah, taht's what i ment
<woprr> no, dvb-t + commercial stations only in some big city areas
<oliv3r> ah, where in DE are you located?
<woprr> ask in #linuxtv or google
<woprr> use /whois woprr
<woprr> BW
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<oliv3r> ah south west DE
<woprr> oliv3r, err d-box1 dvb-c tuner cannot take 256qam without special filters/preamp I've read years before
<oliv3r> awww
<woprr> I've got a hard time getting a TT 2300C used to 256qam, high BER ...
<woprr> = HP nexus-CA
<wingrime> woprr: it depend on reciver ADC range
<wingrime> woprr: two ADC basicly for IQ-demodulation
<oliv3r> OHhhhh, I think I found the TS pins; i think it's PBE; TS0, you loose CSI0 on mux3 then though
<woprr> yes
<woprr> and we need someone experienced with DMA to adapt the new/old dvb buffer core to A20 DMA system
<oliv3r> woprr: so how do you plan to connect the SoC to the module?
<oliv3r> well on olmex it should be easish
<woprr> yes, TSx on the 40 PIN SMT connectors
<woprr> + a hand made pcb carrying the dvb receiver module and the 1.8V supply (phillips cu12616)
<oliv3r> let me grab my olimex and check
<woprr> sorry got some other work to do, bb later
<woprr> thx :)
<woprr> wingrime, ADC is internal auto in CU1216... as I've undestood the sheet "do not connect"
<woprr> or was this a answer to the 256qam issue?
<woprr> -ADC+AGC
<woprr> *argh*
<woprr> bb later
<wingrime> woprr: driver is new, but HW same
<oliv3r> wingrime: what driver?
<wingrime> DMA
<oliv3r> but we don't have a dvb-sunxi driver yet ;)
<woprr> wingrime, I've read high demod quality depends on differental ADC feed, older designs with analog paths don't feed the ADC differential signals
<woprr> oliv3r, depends on DMA driver :D
<woprr> analog tv paths
<wingrime> woprr: many analog stuff
<woprr> like the TT C2300
<oliv3r> GPIO-2 on the olmex board is for TS connector
<woprr> or older
<wingrime> woprr: firstly adc bitness
<woprr> oliv3r, yes in "multi2" mode
<woprr> wingrime, OK
<wingrime> woprr: secondly , niqvist frequency
<wingrime> woprr: 3rd , feed grenerator stability
<woprr> OKOK ^^
<woprr> this is tuner designers business, I'm not chinese ;-)
<woprr> the CU1216-MKIII will work with my provider, even the old with TDA10021 does
<woprr> bb later
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<oliv3r> mripard_: ping
<oliv3r> mripard_: nvm i think i understand ;)
<oliv3r> mripard_: i remember you saying 'register access is bad through structures, but your not doing that, you simple have a 'table' per i2c board and "apply" that table based on the dt
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<mripard_> oliv3r: for the i2c driver?
<mripard_> yeah, the only thing that changed from the marvell to the allwinner controller was the registers offset
<oliv3r> yeah i saw that you first 'cleaned up the driver to accomadate this'
<mripard_> so I just put a structure holding the registers offset for most of the registers
<oliv3r> and then added the sunxi data
<oliv3r> reading as to how the .data property works
<mripard_> it's quite simple for the data field actually
<mripard_> just provide some stuff in the .data field
<oliv3r> you can store anything you want there right?
<mripard_> yep
<mripard_> it's a void*
<oliv3r> i mean, you store the register offsets there
<oliv3r> but i want to store the size of the sid there aswell
<mripard_> so you can do whatever you want with it
<oliv3r> I mean i have SID_KEYS and SID_SIZE now as defines
<oliv3r> but since that changes per SoC, i'll put that information in the .data
<oliv3r> good, that makes things a lot easier
<oliv3r> btw
<oliv3r> the SID key is even bigger then we thought
<oliv3r> there's all the keys
<oliv3r> but there's also the HDCP key etc
<oliv3r> the sid key in total, is 0x200 big
<oliv3r> but now comes 'a' problem
<oliv3r> there's holes
<oliv3r> there's 1 32bit key, that's 16 bit for 'vendor key' (mac or whatever)
<oliv3r> and the other 16 bits are used for 'configuration
<oliv3r> they are read-only (everything in sid is read only)
<oliv3r> but you can read out the status of several 'locks'
<oliv3r> my first thought was to just read everything out
<oliv3r> userspace can deal with the holes
<oliv3r> but then there's some input registers (used when programming) so i guess always return 0 on these undefined registers?
<oliv3r> (I think it does that by default anyway)
<mripard_> hmmmm, I'm not quite sure to follow you on the input registers
<mripard_> 2s
<mripard_> let me look at the datasheet
<oliv3r> page 238 and 239
<oliv3r> i still think we should not do anything with regards to writing with this driver, it should remain read only. if writing is required, we can always develop a specialized tool (its still a high-risc operation imo)
<oliv3r> and requires VDD-EFUSE to supply a programming voltage (we assume still so)
<mripard_> yes, I think we should only focus on reading for now.
<mripard_> I guess you can see it either as one big SID, or several smaller ones here
<mripard_> I don't have any preference
<oliv3r> i will export is as 1 big SID 0x0 - 0x200
<mripard_> seeing it as only one big SID will probably be easier
<oliv3r> and if anybody ever needs it, a userspace tool can be written to parse the sid (into chunks they want)
<mripard_> yep
<oliv3r> e.g. 'parsing sid: HDCP key: 0x1234; boot lock status: off';
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<oliv3r> ok agreed it is :)
<oliv3r> i'll go read your patch a bit more to understand
<oliv3r> mripard_: any reason btw, why olimuxino-micro doesn't have ethernet enabled on a20?
<oliv3r> (the dts)
<mripard_> I didn't tested it yet
<mripard_> and I needed the clocks to do so, which I only finished last week
<mripard_> so, not much technical reasons no :)
<mripard_> only "I need more than 24h in a day"
<mnemoc> who doesn't?
<oliv3r> hahah yeah
<oliv3r> well i made a cubie2 dts i'll send to you/ml as a patch
<oliv3r> i copy pasted it from cubie1 so it has ethernet still in it :p
<mripard_> oliv3r: I already have one :)
<mripard_> for a week or so
<mripard_> but patches for the ethernet are welcome :)
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<oliv3r> mripard_: heh, i did just pull your trees, i must have overlooked it :)
<oliv3r> i need to get something building first anyway, see if i can get my patches ontop of your tree :)
<oliv3r> what is your most complete/recent one?
<oliv3r> god i need to get more organized and structured; working on u-boot, u-boot-a31; sunxi-3.4 and mainline is getting confusing and messy :p
<mripard_> oliv3r: the latest one is probably a20-clocks
<oliv3r> ok i'll use that branch to test things with
<oliv3r> on cubie and olimexino
<oliv3r> only really sucky thing is, that sid is completly empty on both :(
<oliv3r> so we'll see
<oliv3r> mripard_: just out of curiosity, how does this work with a single platform armv7 kernel?
<mripard_> hmmm, well, if the platform has support for the clocks API it uses it, otherwise, it's not compiled in
<oliv3r> but wasn't the future arm plan, to have a signle kernel for several platforms?
<oliv3r> so that #define wouldn't work?
<Turl> oliv3r: yeah, when building multiplatform that gets compiled
<Turl> but some marvell still don't support DT (fully?)
<mripard_> oliv3r: the problem here isn't with a single platform
<Turl> oliv3r: the comment "/* Not all platforms have a clk */" references the IS_ERR check, not the ifdef
<mripard_> it would be with several platforms, with some of them that have clock support, and some that don't
<mripard_> so the config symbol would be selected
<mripard_> but some platforms wouldn't implement clk_enable/clk_disable et al.
<mripard_> but I don't think it's actually a problem either
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<Turl> mripard_: btw, can you push a stable(ish) branch/tag with the A31+A20 clocks stuff when you send v2?
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<Turl> mripard_: also, I think you meant to move the OF_DECLARE macro under the function but it ended up under another function in "clk: sunxi: fix initialization of basic clocks"
<mripard_> right, damn.
<mripard_> a rebase gone wild :)
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<mripard_> Turl: here, I just pushed all the latest branches to github
<mripard_> sunxi-next-a20-clocks has the A10s, A31 and A20 clocks
<Turl> great, thanks mripard_
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<wingrime> Turl: can I get 36 kHz with IR pll
<wingrime> or 38 kHz
<wingrime> Turl: also IR have internal divider
<wingrime> 512 , 256 , 128 , 64
<Turl> wingrime: IR0 clock can just divide, not multiply
<Turl> so you would have to source from other higher clock, like pll5 or pll6
<Turl> err
<Turl> kHz
<Turl> never mind what I just saqid
<Turl> said*
<wingrime> Turl: I simply need more accurate timing for IR RC
<wingrime> Turl: carier for NEC 38 kHz
<wingrime> Turl: RC6 36 kHz
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<Turl> wingrime: how does sun4i-ir does it?
<Turl> do it*
<wingrime> Sample Clock = 23437.5Hz
<arokux> Turl, question: several clocks are muxed together so that the resulting clock get some bigger frequency?
<wingrime> Turl: totaly mess
<Turl> arokux: no, mux is like "input selector"
<Turl> arokux: like when you choose HDMI or VGA or RCA on tv
<arokux> Turl, ok, thanks
<Turl> arokux: if one of the input clocks is higher frequency then you can benefit from that, but they are not combined in any way
<arokux> Turl, so APB1-CLK (in A10) can select among OSC24M, PLL6 or 32KHz?
<Turl> wingrime: IR0 is src/N/M, src is 24MHz, N=1,2,4,8 and m=1,2,3,...,15,16
<Turl> arokux: yes
<arokux> Turl, output of cat /sys/kernel/debug/clk/clk_summary is nice :)
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<Turl> yep
<Turl> that's why I mount debugfs on /d/ :P
<arokux> Turl, is this muxing then configured at power on and persists all the time?
<Turl> yes, it persists
<Turl> I'd need to check if uboot configures it or it's just that way as default on the chip
<arokux> Turl, who configures doesn't matter.
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<arokux> Turl, it would be much more natural to describe the clock tree in dev. tree completely. all factors, divs, shifts etc.
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<Turl> arokux: that's not how device tree rolls though
<oliv3r> wingrime: I would have thought that the IR would do the 38kHz - 36kHz by itself with a clock you feed it. Let me ask the manual
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<arokux> Turl, why enable is 31? :)
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<Turl> arokux: because user manual and AW code say so
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<oliv3r> nah, some chinese got beaten with a stick and made the the wire run to bit 31. His boss his favorite number is 31, so he got beating 32 times, he started with bit0
<arokux> Turl, fair enough..
<Turl> oliv3r: lol, wtf :)
<arokux> Turl, oh.. this is bit #31, not a value 31
<Turl> arokux: yeah, reg |= (1<<31) to enable
<wingrime> oliv3r: mele have RC included?
<Turl> wingrime: yes
<Turl> (at least A10 ones)
<wingrime> Turl: look like I not have no any NEC rc
<Turl> wingrime: no Samsung remote?
<wingrime> there
<wingrime> but it looks like RC6
<wingrime> Turl: ok I find first issue, looks like printf for bytes costs much,than I get fifo overflow
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<wingrime> thats without debug prints
<arokux> Turl, does every SoC has this clock business with the similar tree, muxing, factors etc?
<wingrime> arokux: power consumption
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<arokux> wingrime, I know the reason
<arokux> wingrime, but if everybody has the similar structure?
<Turl> arokux: yes, all SoCs have clocks
<Turl> some more, some less
<wingrime> arokux: in worse case this is internal RC-oscilator
<arokux> Turl, I wonder nobody has added some framework to manage it
<Turl> arokux: uhm
<Turl> arokux: there's the clock framework :) I'm using it
<arokux> Turl, it should be enough to describe everything in dt, like formulas etc. and no C code on SoC side
<Turl> arokux: clocks vary wildly, I don't think that's achievable
<arokux> Turl, I see
<Turl> besides that's not how dt rolls
<arokux> Turl, then maybe a ct - clock tree :)
<mturquette> my ears are burning
<mturquette> all of this talk of clocks in #linux-sunxi!
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<wingrime> mturquette: it very important have clock subsystem work *before* we can write any other drivers
<arokux> mturquette, what would you like to talk about? :p
<Turl> mturquette: :)
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<arokux> Turl, in the emac binding, clocks = <&ahb_gates 17>; for 17 is the number of "ahb_emac".
<arokux> Turl, but how it knows 17 stands for ahb_emac, since there is one number skipped
<arokux> Turl, yes, but 15 is not there.
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<arokux> Turl, and as I understand "<&ahb_gates 17>" means to take clock #17 from the list of those ahb_XXX strings, right?
<Turl> arokux: no, it means "take clock whick is gated with bit #17 on the register"
<Turl> which*
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<mturquette> Turl: i've been working on clk_coordinate_rate(struct clk *clk, unsigned long rate), which can call clk_set_rate and clk_set_parent for multiple clocks for a DVFS transition
<mturquette> Turl: not sure when I'll publish it, but it might be a step towards solving the "coordinated clock rate change" problem
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<Turl> mturquette: how does it work?
<Turl> in other words, how does it get to decide the rates?
<mturquette> so the .coordinate_rate callback would point to a function that knows the details of your clock transition sequence
<mturquette> e.g:
<mturquette> clk_set_rate(periph1, 100000);
<mturquette> clk_set_rate(periph2, 200000);
<mturquette> clk_set_rate(dpll1, 2000000);
<mturquette> and maybe a clk_set_parent in there for good measure ;-)
<mturquette> the DT binding would describe what that clock configuration looks like
<mturquette> for any given operating point we can have multiple clocks each running at some rate
<mturquette> so clk_coordinate_rate would figure out which operating point we want and then just follow the sequence it scraped from DT
<Turl> mturquette: hm
<mturquette> its actually really simple, as clk_coordinate_rate does nothing more than just call existing clk api's in a specific order as specified in DT
<Turl> mturquette: my usecase is as follows, I have a chain of clocks, pll1 -> axi -> ahb -> apb
<mturquette> Here is a DT binding mockup to illustrate:
<mturquette> coordinated-clocks {
<mturquette> /* clock rate parent */
<Turl> where -> reads as "is the parent of"
<mturquette> opp50 =
<mturquette> <&clock-controller 0> 200000 pll1
<mturquette> <&clock-controller 1> 100000 pll1
<mturquette> <&clock-controller 5> 32768 pll2
<mturquette> opp100 =
<mturquette> <&clock-controller 0> 400000 pll1
<mturquette> <&clock-controller 1> 200000 pll1
<mturquette> <&clock-controller 5> 100000 pll1
<mturquette> };
<Turl> mturquette: please use a pastebin next time :)
<mturquette> hastebin 4 life
<mturquette> anyways plz continue with your example
<Turl> mturquette: so, I have those 4 clocks
<Turl> mturquette: if I want to change pll1, I cannot just jump to the target frequency, because the other clocks will go out of operating range
<mturquette> right, you have a sequence to follow
<mturquette> usually specified by silicon vender documentation
<Turl> I haven't seen anything about that on the docs we have, but suppose so
<arokux> Turl, what does "#clocks-cells =<0>;" mean in device node?
<mturquette> Turl: V
<Turl> arokux: that it is a single clock, you would use it as <&clock>
<arokux> Turl, normal device like mmc could be a clock itself?!
<Turl> arokux: mmc node is not going to be a clock
<arokux> but you have #clock-cells = <0> in it :P
<arokux> Turl,
<Turl> mturquette: so, say you have 50 opp in there
<Turl> arokux: check again, that's the mmc clock :)
<Turl> not mmc itself
<Turl> (we don't have a mmc driver yet fwiw)
<arokux> Turl, oh, sorry
<Turl> mturquette: would it take care to traverse the table and apply the changes as indicated?
<Turl> mturquette: like, if from opp100 to opp50, it'd apply pll1, axi, ahb, apb, and from opp50 to 100 it'd do the opposite?
<mturquette> Turl: i had been wondering about that myself. it might not always be safe to simply reverse the order.
<mturquette> I might need to create an "up" and "down" sequence for each operating point
<mturquette> Turl: thanks for the link
<mturquette> btw, i've been trying to abstract out the voltage scaling and coordinated clock rates stuff from cpufreq drivers
<mturquette> Turl: so that platforms like sunxi can use cpufreq-cpu0 isntead
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<Turl> mturquette: yes, that would be nice
<mturquette> thanks for teh links
<arokux> Turl, why emac contains "status=disabled" my research shows, that device won't be probed then. is this true?
<arokux> i remember having internet connection though
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<Turl> arokux: not all sunxi devices have emac, so it is disabled on the parent dtsi and enabled on relevant child dts (status "okay" iirc)
<arokux> Turl, ah.. nice.
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<arokux> Turl, any reason you have named ahb0 module with "mod0"?
<Turl> arokux: hm?
<arokux> you have added sun4i-mod0-clk, this is for managing "AHB Module Clock Gating Register 0"
<arokux> so I wonder whether the more appropriate name would have been sun4i-ahbmo0-clk
<arokux> or so
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<Turl> arokux: eh?
<arokux> Turl, ok, why you have named sun4i-mod0-clk like you did? :)
<Turl> arokux: not sure why are you even mentioning ahb to be honest
<arokux> Turl, I try to understand other clocks in order to add mine
<Turl> :)
<arokux> Turl, are you still working on clocks?
<arokux> because I slowly start to understand them, maybe it is a good idea to add them all......?
<Turl> arokux: yes :) I wouldn't have sent the RFC if I wasn't
<Turl> arokux: having them all would be great, but it takes time and we lack consumers to actually test their implementations
<Turl> it's a bit of a chicken and egg issue
<arokux> Turl, yes, consumers is a problem, i've thought about it too
<Turl> mturquette: did the discussion to extend debugfs or such to be able to enable/set/disable/reparent clocks ever reach anywhere?
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<arokux> Turl, ClkSwich:1; //bit5, usb clock switch <---- what could switch mean?
<arokux> if(MAGIC_VER_C == sw_get_ic_ver()) {
<arokux> aw_ccu_reg->UsbClk.ClkSwich = 1;
<arokux> }
<arokux> probably some hack?
<oliv3r> Turl: why are we talking about clock number 17; why aren't there defines for that? (curious)
<Turl> probably
<Turl> check the user manual arokux
<Turl> oliv3r: I dunno, using defines could be cool
<Turl> oliv3r: I think mripard_ didn't like those much back in the day though
<Turl> maybe he changed his mind :)
<arokux> Turl, I've seen some use of defines for interupts tag
<Turl> yes, defines can be used, we just aren't at the moment
<Turl> I'll ask mripard_ and maybe switch to using them when all this clock work settles
<wingrime> Turl: yep, I want see normal names in /proc/interrupts
<oliv3r> Turl: yeah, but we really hate magic values in the source, and 'its in Doc/somewhere/clocks.txt' isn't really easy to read either
<oliv3r> Turl: well enum or define
<oliv3r> mripard_: ^
<Turl> oliv3r: dt preprocessor can only do define afaik
<Turl> (it's just a preprocessor)
<oliv3r> well i like defines anyway :)
<Turl> wingrime: I don't think that will change when using defines
<oliv3r> SUN4I_CLK_EMAC even if we have to
<wingrime> Turl: GIC contoller show even description
<wingrime> IPI0: 0 CPU wakeup interrupts
<wingrime> sunxis ugly
<wingrime> 33: 90 GIC 33 serial
<oliv3r> wingrime: have you figured out your 36 kHz clock issue?
<wingrime> oliv3r: I only figured that printk takes too much time and interfere
<Turl> wingrime: you will have to ask mripard_
<oliv3r> wingrime: so the /64, /128, /256 and /512 is enough to get the clocks you want?
<wingrime> oliv3r: yes, but is not accurate
<oliv3r> do you have an oscilloscope?
<Turl> wingrime: btw, check sunxi ML, someone wrote another ir driver
<oliv3r> you can hook up your scope to the IR RX or TX pins and you should see the freq.
<oliv3r> Turl: we have IR driver in sunx-3.4
<oliv3r> but that driver is really ugly
<Turl> oliv3r: yeah but another one
<Turl> not the one you unified
<Turl> I think it got lost on the sea of mail and never merged
<oliv3r> Turl: good memory
<Turl> oliv3r: I got a reply from the guy saying if you could merge it :p my memory is crap
<Turl> wingrime: ^
<oliv3r> damn your fast, i was douing the same
<oliv3r> shutko i remember that name
<Turl> yeah he was in here with another nickname, which I don't recall :(
<wingrime> Turl: driver is finished , but No one decoder say that my data correct
<Turl> wingrime: also from .ru
<wingrime> Turl: .ur
<wingrime> Turl: ssvb?
<oliv3r> shutko is wingrime
<wingrime> oliv3r: no
<wingrime> shutko is ssvb
<arokux> ok, sun4i machine can be of 3 types........
<Turl> wingrime: no, it's not ssvb
<oliv3r> wingrime: no, ssvb is sheiria sheisomething (it's hard)
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<oliv3r> no offense intended, i need to practise more
<Turl> oliv3r: all names that are not spanish/english are hard to me :P
<oliv3r> like my last name? :p
<arokux> oliv3r, yes, practiCe*
<arokux> oliv3r, :P
<oliv3r> arokux: depends on UK or US english
<oliv3r> <- dirty yank' english
<Turl> oliv3r: that's actually not that hard (maybe I'm pronouncing it completely wrong though :P)
<oliv3r> it's an austrian name ;)
<arokux> oliv3r, no, but you have used the correct one :)
<oliv3r> i do ok with most names, but most names, you have heard before, so you know how you write it
<oliv3r> ssvb's name is 'unique' to me
<Turl> oliv3r: something like Sheen-a-gl? :P
<oliv3r> arokux: oh god are you a grammar monster?
<arokux> oliv3r, no, google user :D
<oliv3r> arokux: ok i wrote praCtiSe and that's "ok" according to your site
<oliv3r> 3rd example
<oliv3r> practise is UK english appearantly
<arokux> oliv3r, I've said you used correct one
<arokux> oliv3r, as far as i understand it is a noun/verb choice
<wingrime> have we here any people from japan?
<wingrime> so intersing....
<arokux> oliv3r, like advice/advise
<Turl> wingrime: there were some
<oliv3r> arokux: so now you have me confused
<oliv3r> where you correcting me or not? :)
<oliv3r> wingrime: japan is far far away!
<Turl> oliv3r: stuff with s is a verb (practise, advise, etc)
<Turl> oliv3r: with c is a noun (practice, advice, etc)
<oliv3r> i had it right, bby pure chance
<oliv3r> Turl: did you see I killed sun4i
<oliv3r> er
<oliv3r> sun3i
<Turl> oliv3r: saw it
<arokux> machine_is_sun4i is a kernel macro which gets added once you use MACHINE_START macro, right?
<oliv3r> Turl: your memory isn't good at all; you saw shutko's mail
<oliv3r> machine_is_sun4i is EVIL
<Turl> oliv3r: I do not approve, but I will not oppose either
<oliv3r> and will not be used in mainline :p we have dt for that
<oliv3r> Turl: if you want to maintain sun3i, then be my guest to reject the patch ;)
<Turl> oliv3r: as I said, I won't :) I don't have the hardware even
<Turl> but dropping it reduces "googleability" imo
<oliv3r> Turl: problem is, we have no way of knowing the code compiles (well we could check that) but we don't even know if it actually works
<oliv3r> Turl: there's a few references left :p0
<oliv3r> in some readme's
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<oliv3r> Turl: i much rather would have liked it maintained, it's very unifyable
<arokux> oliv3r, EVIL, ok, but what about my statement?
<oliv3r> machine_is_sun4i is a function :)
<oliv3r> that reads out some registers to find out what soc we're running on
<arokux> oliv3r, hm.. grep does not finds it
<arokux> oliv3r, that is why i thought MACHINE_START will define it
<oliv3r> arokux: what branch are you on?
<oliv3r> hansg renamed it i belive
<arokux> sunxi-3.4
<oliv3r> ah, ok should be something like that called
<arokux> well... it's used!
<oliv3r> it's defined in arch/arm/*
<arokux> oliv3r, but buy MACHINE_START, because there are a lot of others machine_is_xxxx
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<oliv3r> arokux: git grep -i machine_is_sun4i doesn't turn up the defeinition of it
<arokux> oliv3r, because there is no definition
<arokux> it is defined by MACHINE_START....
<arokux> ok, my mele_a1000 is sun4i, MAGIC_VER_B.
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<oliv3r> that's what we use now
<oliv3r> i think we don't use machine_is_sun4i anymore
<arokux> oliv3r, push it to sunxi-3.4 then...
<oliv3r> it's in stage/sunxi-3.4
<oliv3r> sunxi-3.4 is old and needs to be updated badly
<oliv3r> once stage/sunxi-3.4 is 'ok'
<arokux> oliv3r, so would you recommend to use stage/sunxi-3.4 then?
<oliv3r> well if you rewrite/fix USB controller then you'll have to push your patches into that repo anyway
<oliv3r> :)
<oliv3r> so yeah, using that as reference is probably your best bet
<arokux> oliv3r, ok!
<arokux> Turl, setting reg, you put 4 as number of bytes, however only 1 is really used. is there any requirement on alignment or smth?
<oliv3r> arokux: most registers are bound to 32bit read/write
<Turl> arokux: regs are 32 bit wide (ie 4 bytes)
<oliv3r> undefined behavior happens if you read it otherwise
<oliv3r> hence, the manual states all registers in 32bit chunks
<Turl> so 1 reg = 4 bytes
<oliv3r> nn all
<arokux> Turl, ok. how do you think, how fast should a usb clock be?
<arokux> OHCIClkSrc --- 0-(PLL6)/25, 1-PLL6 sample 24Mhz to generate 48Mhz
<arokux> but in the manual: usb_clk usb 480MHz Sourced from the PLL
<Turl> arokux: you take the source and you multiply/divide it
<Turl> look around, you'll see other tunables
<arokux> in the code there is also: aw_ccu_reg->UsbClk.OHCIClkSrc = 0;
<arokux> so it is then (PLL6)/25
<arokux> Turl, which is exactly 480MHz!
<arokux> :)
<arokux> (PLL6 is 1.2GHz)
<arokux> Turl, do you think "1-PLL6 sample 24Mhz to generate 48Mhz" actually means to sample a multiplier from the formula (24MHz*N*K)/2?
<arokux> also, this option (setting OHCIClkSrc to 1) seems not to be used in code, so is it ok, if I hard code it to 0?
<mturquette> Turl: it reached a dead end
<mturquette> Turl: there were a few ways to do it, but none that i felt comfortable with
<mturquette> Turl: too easy for device integrators *cough* android *cough* to abuse
<arokux> anybody knows what shift and width could mean in clock context?
<arokux> shift is, I suppose, division.
<arokux> width is multiplication then?
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<arokux> arokux, never mind, i've figured it out
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<Turl> arokux: width is.. width :p in bits
<Turl> and shift is how much <<
<arokux> Turl, yes.. shift is normally offset, that is why it was confusing
<Turl> mturquette: :/ they already do worse than that
<Turl> mturquette: *cough* qcom's thermald *cough*
<mturquette> Turl: yeah i used to ship Android devices for a living back when I worked at TI, so I know the hacks by heart
<mturquette> and that's why i never saw a solution for userspace control of clocks that i felt comfortable merging upstream
<Turl> mturquette: ti's stack is great when you look it with qcom's on the side
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<mturquette> yeah i just read that qcom has 37k lines of devicetree files
<mturquette> all done in-house. i'd be interested to see what that looks like
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<Turl> same
<Turl> they're using 3.4 or so on shipping products though, not much DT on there
<arokux> dev tree of 37k lines.. is that good or bad? :)
<Turl> arokux: I bet it's >1 :)
<arokux> Turl, what?
<Turl> many device trees, not just 1
<arokux> >1?
<hno> depen on how much hardware you have to describe. It it' a single tablet then...
<arokux> ah
* hno thinks so to.
<arokux> dev tree should come out of hardware design software....:)
<arokux> hno, Turl, do you guys use tftp from uboot?
<Turl> arokux: yes
<arokux> Turl, cubieboard?
<arokux> Turl, and u-boot-next?
<Turl> arokux: yes, and A10S-OLinuXino
<Turl> arokux: normal uboot, I dunno
<Turl> hno: ^
<arokux> it kind of crashed to me (mele a1000). got not responsive.
<Turl> crashed how?
<arokux> Turl, got not responsive.
<arokux> Turl, also maybe printed some garbage
<arokux> do not remember exactly
<Turl> mele has a gpio you need to enable the phy I think
<Turl> hno: ^ is that implemented on uboot?
<arokux> Turl, yep, it was on
<arokux> Turl, never mind, neeed to try it out once again
<arokux> Turl, I need a piece of advice
<arokux> how do you think?
<arokux> Turl, notice, there is gating for PHY as well as for OHCI0 and OHCI1..
<Turl> arokux: looks like 3 gate clocks behind a mux to me
<arokux> Turl, i.e. this one is a parent and needs 3 children...
<Turl> arokux: there would be a parent, say, "usb", with 3 children, "ohci0", "ohci1" and "phy"
<Turl> dt-wise it could be a single usb node with 3 outputs
<Turl> arokux: I can implement them for you if you need them
<arokux> Turl, let me do this I think I have all the pieces now
<Turl> arokux: ok :)
<arokux> Turl, :) thanks