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<wingrime>
oliv3r: ping
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<oliv3r>
wingrime pong
<oliv3r>
if CIR is RC, then FIR and MIR are less ipmortant
<rm>
well said
<rm>
(:D)
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<Ehsand>
hipboi_: hi
<Ehsand>
hipboi_: /msg ?
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<mripard_>
Turl: wingrime: devm_clk_get is a managed clk_get
<mripard_>
that means that the clocks will be "garbage collected" when the driver is removed
<oliv3r>
mripard_: dirty words!
<oliv3r>
'garbage collected', yuk :p
<mripard_>
now, clk_get will either use of_clk_get or clk_get_sys to actually retrieve the reference to the clock you want
<FR^2>
"say something dirty to me!" - "kitchen! bathroom! ..."
<mripard_>
so yeah, bottom line is that you should devm_clk_get, except if you have a good reason not to.
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<oliv3r>
FR^2: GARBAGE COLLECTOR!
<FR^2>
oliv3r: garbage first, mark-and-sweep or mark-and-compact?
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<oliv3r>
:p
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<arokux1>
hi
<oliv3r>
lo
<mripard_>
arokux1: hi :)
<oliv3r>
mnemoc: patches! :)
<hno>
I think we might need a patchwork.
<oliv3r>
hopefully on the new server things like that would be nice
<mnemoc>
ack
<hno>
oliv3r, patch 3/3 have a poor subject. Unifying what?
<mnemoc>
I got the new dedicated IP today
<oliv3r>
Infrared
<utente>
hi all
<oliv3r>
hmm i don't see 1/3 yet on ML
<hno>
I know, but git log --pretty=oneline don't..
<oliv3r>
but yes, i need to write better commit messages :)
<hno>
I see all three + cover letter.
<oliv3r>
mnemoc: want me to resend or can you edit the file before merging (just append ' IR')
<utente>
im using xchat, i can receive files but my peer cannto recdive mine. i dunbo if problem is me or him, can i send a t4est file to someone?
<hno>
utente, you most likely are behind a NAT router that don't handle DCC.
<oliv3r>
mnemoc: hansg wants to pull it into his branch, want to pull it from him?
<utente>
hno... it could be. can i try to send a test pdf to you, hno?
<oliv3r>
mnemoc: if i let hansg pull; i'll edit the commit message before pushing it
<utente>
hno, can i?
<hno>
utente, I am behind double NAT and doubt DCC work for me..
<utente>
i can tra to sent? in worse case, it just fail.
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<oliv3r>
mnemoc: i pushed it to github so you could pull from there
<hno>
utente, you can try..
<oliv3r>
or hansg; or both :)
<hno>
oliv3r, yes that's the beauty of git.
<utente>
hno, ok
<utente>
no it fail.
<oliv3r>
hno: i love git; when i started it was 'hard' to grasp the changes from svn, but i like it lots. just need to get better at it, ti's complexity makes it hard to master :)
<mnemoc>
oliv3r: I'm setting up my desktop at work. I'll try to get into that soon
<oliv3r>
mnemoc: no rush :)
<oliv3r>
still don't see 1/3 on the ML :S
<oliv3r>
stupid google groups
<mnemoc>
hopefully i'll setup mailman soon too
<mnemoc>
and leave the google groups thing for users
<oliv3r>
:D
<oliv3r>
mnemoc: you got an office and everything now? collegues too?
<hno>
oliv3r, yes.. and svn is no fun at all when you have got used to git & bzr. But. need to learn git submodules better.
<oliv3r>
i like how the sunxi-bsp is setup with the submodules
<mnemoc>
oliv3r: yes, 7 people total... and a sock filtered coffee machine
<oliv3r>
but yeah, i'm not all into it either
<oliv3r>
mnemoc: coffee, yuk :p
<oliv3r>
what OS is on the desktop?
<hno>
mnemoc, maybe we should get a sysadmin for linux-sunxi?
<mnemoc>
hno: you'll get your key there as soon as the lxc is installed and network configured
<mnemoc>
this evening hopefully, now that I got the extra IP
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<oliv3r>
if you need any help, just let us know :)
<mnemoc>
i'm (slowly) getting things under control. but the (tested) pull branches are a GREAT help
<hno>
gah... 3G networks.. randomly giving you a new IP without asking.
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<hno>
mnemoc, good to hear that.
<oliv3r>
hno: ack
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<hno>
what was the last message you saw from me (before the 3G one)
<mnemoc>
11:39:07 < hno> mnemoc, maybe we should get a sysadmin for linux-sunxi?
<arokux1>
I'm trying to understand what happens on major trees.. what about Hans de Goede, he is trying to assemble his own tree for fedora? i've got the feeling that his tree contains more patches than stage/sunxi-3.4
<hno>
ok.
<hno>
arokux1, he is reviewing and staging patches in general.
<arokux1>
hno, what is the path for those patches to lend in kind of central linux-sunxi tree on github?
<hno>
arokux1, there is no single path, but all path share the need for a review on linux-sunxi mailinglist.
<hno>
and most times it's mnemoc that is the final gatekeeper for pushing into the linux-sunxi repo after review.
<hno>
a process that is a lot easier if the one doing review first pushes to a personal repository, such as what hansg is doing.
<arokux1>
hno, I see, thanks
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<_hipboi_>
Ehsand, ping
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<_hipboi_>
mnemoc!!
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<arokux1>
_hipboi_, any news on cubietruck? :P
<oliv3r>
alllready gone
<_hipboi_>
arokux1, still preparing production
<_hipboi_>
network is not good here
<oliv3r>
:(
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<oliv3r>
i don't see wingrime's cedarX unification in stage/sunxi-3.4 yet :(
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<woprr>
re
<woprr>
still no delivery from olimex UK but I've remembered ordering from another Britain with "Royal Mail (Small Packets)" a year before, could take 14 days to DE
<woprr>
so I assume it's not airmail, cannot find the RM product "small packets"
<woprr>
shipping cost the other seller noted is £0,99, too low for airmail
<FR^2>
woprr: I ordered stuff for about 100 EUR and didn't have any shipping costs
<oliv3r>
oh i would ;)
<woprr>
> 100 EUR maybe shipping free
<FR^2>
woprr: indeed ;)
<FR^2>
woprr: "Kostenloser Versand ab 100€ innerhalb Deutschlands"
<FR^2>
I ordered some power supplies, a breadboard for 3,20 EUR, the cubieboard2 and a case. That way I came above the 100 EUR. But if you don't have anything you could order that actually makes sense, ...
<FR^2>
woprr: Wait a second... 3,50 EUR shipping costs via DHL
<oliv3r>
(i don't know where to place the hardware and its functionality)
<woprr>
CU1216 types receivers, tuner and demod included, ~30 manual processable pins direct to Ax0 TSx port
<oliv3r>
CU1216 what?
<oliv3r>
and more what?
<woprr>
receiver module
<woprr>
philips
<oliv3r>
ah ok
<woprr>
google picture
<oliv3r>
ohh those old fashioned big cans
<oliv3r>
i haven't seen the pin multiplex for it actually
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<woprr>
no I've got the latest TDA10023 from QQBOX modules on ebay, silicon tuners are crap and not manual processable without lab or lead factory, too small mil pins, BGA etc
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<oliv3r>
woprr: very true
<oliv3r>
ok so tuner i know what that is
<oliv3r>
then we have the demodulator, does the 'ts' do that bit?
<oliv3r>
and usually you have a 'bridge' that connects the tuner and the demodulator to the PCI/USB bus
<oliv3r>
that much I know
<woprr>
for dvb-s 1 I've found 2 sharp receiver modules we've already got linux drivers for, but I will use the BSBSE1 from an old TT S2300, it has the better STV0299 demod, sharp older the STV0288
<oliv3r>
so is the 'ts' unit only the bridge? or does it combined that (in a platform way)
<oliv3r>
i actually have an old TT-1500 DVB-T card, i could 'borrow' that tuner :)
<woprr>
those receiver modules come with the Ax0 compatible "dvb -interface" called in some tuner datasheets
<oliv3r>
what is Ax0? I doubt they mean A10 and A20 :p
<woprr>
can be direct attached to Ax0 TSx
<woprr>
A10/20 :)
<woprr>
A31 3 TS controllers? ;-)
<woprr>
TSC
<oliv3r>
TDA10046H is the tuner i have
<oliv3r>
maybe i can repurpse it
<woprr>
yes thats a dvb-t
<woprr>
a very good
<woprr>
but not dvb-T2 ?
<oliv3r>
not sure, don't think so
<woprr>
I would prefer the TDA10086 for dvb-s but not seen in any receiver module
<woprr>
...manually leadable ;)
<oliv3r>
oh i even have a few dvb-s receiverss with tuners
<oliv3r>
nokia dbox-1 and dbox-2 dvb-s
<oliv3r>
and i have a dbox-1 dvb-c
<oliv3r>
i smell harvestable tuners :)
<woprr>
eheh ok, You've got it all!
<woprr>
happy recycling
<oliv3r>
yeah but don't know if i have time to actually build anything
<oliv3r>
and b) don't know if i have the willpower to build as i have no use for it right now :p
<oliv3r>
then again, connecting a tuner to the a20-olimex sounds like a fun project
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<oliv3r>
do keep the info up on linuxtv.org wiki ;)
<oliv3r>
maybe i'll build it too :)
<woprr>
dvb-c is easy to connect, dvb-s needs extra LNB/diseqc circuits and power supply
<oliv3r>
ah yes
<oliv3r>
dvb-t should be easy too
<woprr>
where to put SMT connector dvb-receiver extensions modules in this wiki :?
<woprr>
yes dvb-t too
<oliv3r>
good question, just make a new page ;)
<woprr>
makes no sense in my region only 12 state tv channels and you need a roof yagi
<oliv3r>
trying to find the tda10046 pinout
<woprr>
dvb-t transmitters > 50km away
<oliv3r>
where is your region? i thought germany was pretty well dvb-t equipped
<woprr>
you dont need the chips pinout, you only need the module pinout
<oliv3r>
well yeah, taht's what i ment
<woprr>
no, dvb-t + commercial stations only in some big city areas
<oliv3r>
ah, where in DE are you located?
<woprr>
ask in #linuxtv or google
<woprr>
use /whois woprr
<woprr>
BW
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<oliv3r>
ah south west DE
<woprr>
oliv3r, err d-box1 dvb-c tuner cannot take 256qam without special filters/preamp I've read years before
<oliv3r>
awww
<woprr>
I've got a hard time getting a TT 2300C used to 256qam, high BER ...
<woprr>
= HP nexus-CA
<wingrime>
woprr: it depend on reciver ADC range
<wingrime>
woprr: two ADC basicly for IQ-demodulation
<oliv3r>
OHhhhh, I think I found the TS pins; i think it's PBE; TS0, you loose CSI0 on mux3 then though
<woprr>
yes
<woprr>
and we need someone experienced with DMA to adapt the new/old dvb buffer core to A20 DMA system
<oliv3r>
woprr: so how do you plan to connect the SoC to the module?
<oliv3r>
well on olmex it should be easish
<woprr>
yes, TSx on the 40 PIN SMT connectors
<woprr>
+ a hand made pcb carrying the dvb receiver module and the 1.8V supply (phillips cu12616)
<oliv3r>
let me grab my olimex and check
<woprr>
sorry got some other work to do, bb later
<woprr>
thx :)
<woprr>
wingrime, ADC is internal auto in CU1216... as I've undestood the sheet "do not connect"
<woprr>
or was this a answer to the 256qam issue?
<woprr>
-ADC+AGC
<woprr>
*argh*
<woprr>
bb later
<wingrime>
woprr: driver is new, but HW same
<oliv3r>
wingrime: what driver?
<wingrime>
DMA
<oliv3r>
but we don't have a dvb-sunxi driver yet ;)
<woprr>
wingrime, I've read high demod quality depends on differental ADC feed, older designs with analog paths don't feed the ADC differential signals
<woprr>
oliv3r, depends on DMA driver :D
<woprr>
analog tv paths
<wingrime>
woprr: many analog stuff
<woprr>
like the TT C2300
<oliv3r>
GPIO-2 on the olmex board is for TS connector
<woprr>
or older
<wingrime>
woprr: firstly adc bitness
<woprr>
oliv3r, yes in "multi2" mode
<woprr>
wingrime, OK
<wingrime>
woprr: secondly , niqvist frequency
<wingrime>
woprr: 3rd , feed grenerator stability
<woprr>
OKOK ^^
<woprr>
this is tuner designers business, I'm not chinese ;-)
<woprr>
the CU1216-MKIII will work with my provider, even the old with TDA10021 does
<woprr>
bb later
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<oliv3r>
mripard_: ping
<oliv3r>
mripard_: nvm i think i understand ;)
<oliv3r>
mripard_: i remember you saying 'register access is bad through structures, but your not doing that, you simple have a 'table' per i2c board and "apply" that table based on the dt
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<mripard_>
oliv3r: for the i2c driver?
<mripard_>
yeah, the only thing that changed from the marvell to the allwinner controller was the registers offset
<oliv3r>
yeah i saw that you first 'cleaned up the driver to accomadate this'
<mripard_>
so I just put a structure holding the registers offset for most of the registers
<oliv3r>
and then added the sunxi data
<oliv3r>
reading as to how the .data property works
<mripard_>
it's quite simple for the data field actually
<mripard_>
just provide some stuff in the .data field
<oliv3r>
you can store anything you want there right?
<mripard_>
yep
<mripard_>
it's a void*
<oliv3r>
i mean, you store the register offsets there
<oliv3r>
but i want to store the size of the sid there aswell
<mripard_>
so you can do whatever you want with it
<oliv3r>
I mean i have SID_KEYS and SID_SIZE now as defines
<oliv3r>
but since that changes per SoC, i'll put that information in the .data
<oliv3r>
good, that makes things a lot easier
<oliv3r>
btw
<oliv3r>
the SID key is even bigger then we thought
<oliv3r>
there's all the keys
<oliv3r>
but there's also the HDCP key etc
<oliv3r>
the sid key in total, is 0x200 big
<oliv3r>
but now comes 'a' problem
<oliv3r>
there's holes
<oliv3r>
there's 1 32bit key, that's 16 bit for 'vendor key' (mac or whatever)
<oliv3r>
and the other 16 bits are used for 'configuration
<oliv3r>
they are read-only (everything in sid is read only)
<oliv3r>
but you can read out the status of several 'locks'
<oliv3r>
my first thought was to just read everything out
<oliv3r>
userspace can deal with the holes
<oliv3r>
but then there's some input registers (used when programming) so i guess always return 0 on these undefined registers?
<oliv3r>
(I think it does that by default anyway)
<mripard_>
hmmmm, I'm not quite sure to follow you on the input registers
<mripard_>
2s
<mripard_>
let me look at the datasheet
<oliv3r>
page 238 and 239
<oliv3r>
i still think we should not do anything with regards to writing with this driver, it should remain read only. if writing is required, we can always develop a specialized tool (its still a high-risc operation imo)
<oliv3r>
and requires VDD-EFUSE to supply a programming voltage (we assume still so)
<mripard_>
yes, I think we should only focus on reading for now.
<mripard_>
I guess you can see it either as one big SID, or several smaller ones here
<mripard_>
I don't have any preference
<oliv3r>
i will export is as 1 big SID 0x0 - 0x200
<mripard_>
seeing it as only one big SID will probably be easier
<oliv3r>
and if anybody ever needs it, a userspace tool can be written to parse the sid (into chunks they want)
<Turl>
mripard_: also, I think you meant to move the OF_DECLARE macro under the function but it ended up under another function in "clk: sunxi: fix initialization of basic clocks"
<mripard_>
right, damn.
<mripard_>
a rebase gone wild :)
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<mripard_>
Turl: here, I just pushed all the latest branches to github
<mripard_>
sunxi-next-a20-clocks has the A10s, A31 and A20 clocks
<Turl>
great, thanks mripard_
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<wingrime>
Turl: can I get 36 kHz with IR pll
<wingrime>
or 38 kHz
<wingrime>
Turl: also IR have internal divider
<wingrime>
512 , 256 , 128 , 64
<Turl>
wingrime: IR0 clock can just divide, not multiply
<Turl>
so you would have to source from other higher clock, like pll5 or pll6
<Turl>
err
<Turl>
kHz
<Turl>
never mind what I just saqid
<Turl>
said*
<wingrime>
Turl: I simply need more accurate timing for IR RC
<wingrime>
Turl: carier for NEC 38 kHz
<wingrime>
Turl: RC6 36 kHz
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<Turl>
wingrime: how does sun4i-ir does it?
<Turl>
do it*
<wingrime>
Sample Clock = 23437.5Hz
<arokux>
Turl, question: several clocks are muxed together so that the resulting clock get some bigger frequency?
<wingrime>
Turl: totaly mess
<Turl>
arokux: no, mux is like "input selector"
<Turl>
arokux: like when you choose HDMI or VGA or RCA on tv
<arokux>
Turl, ok, thanks
<Turl>
arokux: if one of the input clocks is higher frequency then you can benefit from that, but they are not combined in any way
<arokux>
Turl, so APB1-CLK (in A10) can select among OSC24M, PLL6 or 32KHz?
<Turl>
wingrime: IR0 is src/N/M, src is 24MHz, N=1,2,4,8 and m=1,2,3,...,15,16
<Turl>
arokux: yes
<arokux>
Turl, output of cat /sys/kernel/debug/clk/clk_summary is nice :)
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<Turl>
yep
<Turl>
that's why I mount debugfs on /d/ :P
<arokux>
Turl, is this muxing then configured at power on and persists all the time?
<Turl>
yes, it persists
<Turl>
I'd need to check if uboot configures it or it's just that way as default on the chip
<arokux>
Turl, who configures doesn't matter.
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<arokux>
Turl, it would be much more natural to describe the clock tree in dev. tree completely. all factors, divs, shifts etc.
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<Turl>
arokux: that's not how device tree rolls though
<oliv3r>
wingrime: I would have thought that the IR would do the 38kHz - 36kHz by itself with a clock you feed it. Let me ask the manual
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<arokux>
Turl, why enable is 31? :)
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<Turl>
arokux: because user manual and AW code say so
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<oliv3r>
nah, some chinese got beaten with a stick and made the the wire run to bit 31. His boss his favorite number is 31, so he got beating 32 times, he started with bit0
<arokux>
Turl, fair enough..
<Turl>
oliv3r: lol, wtf :)
<arokux>
Turl, oh.. this is bit #31, not a value 31
<Turl>
arokux: yeah, reg |= (1<<31) to enable
<wingrime>
oliv3r: mele have RC included?
<Turl>
wingrime: yes
<Turl>
(at least A10 ones)
<wingrime>
Turl: look like I not have no any NEC rc
<Turl>
wingrime: no Samsung remote?
<wingrime>
there
<wingrime>
but it looks like RC6
<wingrime>
Turl: ok I find first issue, looks like printf for bytes costs much,than I get fifo overflow
<arokux>
Turl, and as I understand "<&ahb_gates 17>" means to take clock #17 from the list of those ahb_XXX strings, right?
<Turl>
arokux: no, it means "take clock whick is gated with bit #17 on the register"
<Turl>
which*
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<mturquette>
Turl: i've been working on clk_coordinate_rate(struct clk *clk, unsigned long rate), which can call clk_set_rate and clk_set_parent for multiple clocks for a DVFS transition
<mturquette>
Turl: not sure when I'll publish it, but it might be a step towards solving the "coordinated clock rate change" problem
<Turl>
in other words, how does it get to decide the rates?
<mturquette>
so the .coordinate_rate callback would point to a function that knows the details of your clock transition sequence
<mturquette>
e.g:
<mturquette>
clk_set_rate(periph1, 100000);
<mturquette>
clk_set_rate(periph2, 200000);
<mturquette>
clk_set_rate(dpll1, 2000000);
<mturquette>
and maybe a clk_set_parent in there for good measure ;-)
<mturquette>
the DT binding would describe what that clock configuration looks like
<mturquette>
for any given operating point we can have multiple clocks each running at some rate
<mturquette>
so clk_coordinate_rate would figure out which operating point we want and then just follow the sequence it scraped from DT
<Turl>
mturquette: hm
<mturquette>
its actually really simple, as clk_coordinate_rate does nothing more than just call existing clk api's in a specific order as specified in DT
<Turl>
mturquette: my usecase is as follows, I have a chain of clocks, pll1 -> axi -> ahb -> apb
<mturquette>
Here is a DT binding mockup to illustrate:
<mturquette>
coordinated-clocks {
<mturquette>
/* clock rate parent */
<Turl>
where -> reads as "is the parent of"
<mturquette>
opp50 =
<mturquette>
<&clock-controller 0> 200000 pll1
<mturquette>
<&clock-controller 1> 100000 pll1
<mturquette>
<&clock-controller 5> 32768 pll2
<mturquette>
opp100 =
<mturquette>
<&clock-controller 0> 400000 pll1
<mturquette>
<&clock-controller 1> 200000 pll1
<mturquette>
<&clock-controller 5> 100000 pll1
<mturquette>
};
<Turl>
mturquette: please use a pastebin next time :)
<mturquette>
hastebin 4 life
<mturquette>
anyways plz continue with your example
<Turl>
mturquette: so, I have those 4 clocks
<Turl>
mturquette: if I want to change pll1, I cannot just jump to the target frequency, because the other clocks will go out of operating range
<mturquette>
right, you have a sequence to follow
<mturquette>
usually specified by silicon vender documentation
<Turl>
I haven't seen anything about that on the docs we have, but suppose so
<arokux>
Turl, what does "#clocks-cells =<0>;" mean in device node?