<anarsoul|2>
vagrantc: you've got bitten by SPL size limit :)
<vagrantc>
apritzel: thanks, will try
<vagrantc>
the mainline pine64_plus with the same patches applied builds fine, fwiw, though i'm not surprised that pinebook has more hardware and thus more code...
<apritzel>
vagrantc: but that should not apply to the SPL
<apritzel>
vagrantc: what compiler do you have?
<apritzel>
vagrantc: GCC 5.x or earlier generate larger code
<anarsoul|2>
vagrantc: pinebook needs axp803 driver to enable some regulators
<anarsoul|2>
for LCD to power up
<apritzel>
which could be done in ATF as well, I guess ...
<apritzel>
anarsoul|2: does the AXP compile into the SPL as well?
<anarsoul|2>
apritzel: yes
<vagrantc>
apritzel: i think gcc-7, but maybe gcc-6
<anarsoul|2>
apritzel: could be done in SPL, but that would require a separate ATF image for pinebook...
<apritzel>
anarsoul|2: I have some cool new feature in ATF: I read the SPL header from SRAM A1 and figure out the DT name
<apritzel>
so ATF can do board specific fixups
<apritzel>
for instance I now change the DRAM voltage for Pine64s only
* vagrantc
finally got pine64+ working with u-boot spl!
<vagrantc>
which is why i was hoping to get pinebook working too... :)
<vagrantc>
i've got some ancient ATF build ... maybe it's time to try and build a new one
<anarsoul|2>
apritzel: cool
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<anarsoul|2>
vagrantc: nice, I'll look into it
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<anarsoul|2>
oops, I meant apritzel: nice, I'll look into it :)
<apritzel>
vagrantc: definitely, I fixed some bugs lately
<vagrantc>
apritzel: cool.
<anarsoul|2>
vagrantc: well, it works fine for me
<anarsoul|2>
with my branch
<vagrantc>
anarsoul|2: i've applied the patches from your branch to v2017.11 in the debian package, and built that way ... there may be some compiler flags passed that are different or something
<wink__>
Hi folks,I m an engineer from Allwinner, happy to announce that the lastest BSP (with Linux 4.4) of H3 was released, github page is https://github.com/Allwinner-Homlet
<apritzel>
wens: yeah, but you need someone to be pesky and push that
<wens>
apritzel: looks like it landed
<wens>
wink__: thanks, though why the new project name?
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<anarsoul|2>
wink__: any plans for 4.4 for A64?
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<vagrantc>
yay!
<vagrantc>
u-boot 2017.11 on pinebook
<icenowy[m]>
anarsoul|2: he's for BU3
<icenowy[m]>
so not responsible for A64
<anarsoul|2>
vagrantc: :)
<anarsoul|2>
icenowy[m]: what's BU3?
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<vagrantc>
oh, even see output on the screen... not used to that!
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<wink__>
anarsoul|2:A64 hasn't a Linux 4.4 plan yet, the next plan is for H6.
<anarsoul|2>
wink__: I see, thanks for response!
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<vagrantc>
hrm. eMMC doesn't seem stable enough to load an initrd...
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<anarsoul|2>
vagrantc: yeah, I had the same issue with eMMC, but it went away after I charged pinebook
<anarsoul|2>
so if yours at ~5% you may need to charge it :)
<anarsoul|2>
vagrantc: it's unstable in both u-boot and linux, so could be a hardware issue
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<vagrantc>
oh yeah, this has had power, but probably no supported kernel or u-boot to charge it
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<vagrantc>
hmmm... seems to think it's at 100% battery
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<smaeul>
wink[AW]: any chance of releasing arisc firmware source or toolchain?
<vagrantc>
seems to read from microSD just fine...
<wink[AW]>
exit
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<aalm>
:D
<aalm>
was that "oh, tough Q, better run"
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* vagrantc
realizes icenowy's sunxi64-4.14-rc6 also contains the pinebook patchsets
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<anarsoul>
vagrantc: and mine 4.15-rc1 also contains pinebook patches ;)
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<oliv3r>
plaes: ping
<silviop>
plaes: have you added support for dual channel lvds in kernel drm ?
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<derRichard>
hi
<derRichard>
my a20 board resets sometimes. is there a status register i can query in uboot after a reset to get the reason?
<qschulz>
mainline or vendor u-boot?
<wens>
nope
<willmore>
KotCzarny, wasn't 4.14 also getting 6 years?
<derRichard>
qschulz: mainline
<derRichard>
both kernel and uboot
<derRichard>
but i can switch to vendor uboot, if needed
<KotCzarny>
willmore: yeah, but i suspect when the 6 years was announced 4.14 wasnt existing yet
<KotCzarny>
so most likely people worked what they had (ie. 4.4)
<willmore>
I'm just saying, if you're working on a 'use a more current kernel' effort right now, the smart goal is clearly 4.14 with the hope of doing that tiny bit extra at the end to actually mainline it. :) Maybe I'm just too hopeful.
<KotCzarny>
it might change once 4.15 gets released
<willmore>
brtlin is right, Greg posted recently specifically refuting the 6 years for 4.14. At least for now, KotCzarny there might still be hope. So, given that, I can completely see the 4.4 reasoning.
<willmore>
Then again, if you go mainline, you get support forever. Just saying. ;)
<KotCzarny>
forever*: some restrictions apply, you abandon your driver with no maintainers, support gets removed
<KotCzarny>
;)
<willmore>
Of course. :)
<KotCzarny>
hmm, offtopic, did anything change in 4.13+ ? f->f_op->read method seems missing
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<plaes>
oliv3r: pong!
<plaes>
silviop: nope, haven't had time to play with this stuff at all
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<zzeroo>
Hi, I try to enable my touch screen. The screen is connected via lvds. After updateing my mainline kernel 4.6 to 4.13 the touch is not working. Now my question. Do I have to recompile u-boot after changing the device tree file?
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<zzeroo>
To save time ATM I extract the devicetree, edit it, and recompile afterwards `dtc -O dts` && edit the .dts && `dtc -O dtb ...` Is this enough?
<KotCzarny>
i think there should be a page which lists socs and the bricks they are made of
<KotCzarny>
for starters
<apritzel>
zzeroo: then: fdt set /soc/somenodename property <value>
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<KotCzarny>
would require to identify and name those bricks somehow
<apritzel>
I think the A63 is to the H6 what the A64 is to the H5
<apritzel>
weird numbering, though ;-)
<apritzel>
A series have less USB (because you don't need many for a tablet)
<willmore>
KotCzarny, they left out the discovery that PCI has. That wasn't considered important as SoCs were supposed to be fixed things--the configuration would be baked in. Thanks ARM. :(
<willmore>
apritzel, I solved the numbering!!!! Sum the digits. They have to add up to 15 within and A and H pair.
<apritzel>
willmore: there is discovery in ARM IP, see IIDR registers in PL011 and the GIC, for instance
<zzeroo>
apritzel: `fdt addr 0x43000000` results in `libfdt fdt_check_header(): FDT_ERR_BADMAGIC` where do I find the correct addr?
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<apritzel>
zzeroo: did you load the DT already?
<apritzel>
(to $fdt_addr_r)
<zzeroo>
apritzel: my boot.cmd contains something like that: "load mmc 0:1 0x43000000 ${fdtfile}"
<apritzel>
zzeroo: yes, and afterwards you tell U-Boot about the DT with "fdt addr 0x43000000"
<apritzel>
zzeroo: given that there is something at $fdtfile
<willmore>
apritzel, For some hardware, yes, but the serial ports? Ethernet? etc.
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<apritzel>
willmore: PL011 is serial
<apritzel>
willmore: think about how to do this nicely and you will end up at something like device tree
<apritzel>
willmore: also the AMBA bus can discover devices
<willmore>
apritzel, I will have to look into that.
<apritzel>
willmore: check the final part of drivers/tty/serial/amba-pl011.c
<tkaiser>
apritzel: Which reminds me to search in the new H3 kernel 4.4 BSP for fex ;)
<willmore>
apritzel, thanks.
<apritzel>
willmore: but at the end what PCI offers is not flexible enough for a fine grained SoC: no clocks, no pin multiplex pin descriptions, ...
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<tkaiser>
21 hits for sys_config.fex in the kernel code drop :)
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<zzeroo>
apritzel: Thanks this works. This means editing the dtb is enought. I dont have to recompile something, right?
<apritzel>
tkaiser: what did you expect: it looks more like a forward port from 3.10 to [lsk-v4.4-17.03 ~ lsk-v4.4-17.05]
<tkaiser>
Yes, unfortunately.
<apritzel>
zzeroo: exactly, just use the fdt commands, then pass the original address to the kernel
<apritzel>
zzeroo: you might want to insert "fdt resize" from time to time
<apritzel>
zzeroo: in case you add properties or nodes
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<icenowy[m]>
yes
<icenowy[m]>
still the familiar taste in the 4.4 BSP
<zzeroo>
apritzel: Thank you, this saves time again. But this thing is so huge ^^ I've to read some more docs about ;)
<willmore>
apritzel, true. The 'what does the peripherial do with the signals' part is completely absent from PCI.
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<apritzel>
willmore: which is not PCI to blame for, really, as it was more designed for cards in slots, which have their own clocks and there is no need for pin multiplexing, for instance
<apritzel>
willmore: Cavium actually hides their platform devices behind a PCI config space (at least in the ThunderX1)
<zzeroo>
My old device tree contains "wake-gpios = <7 7 GPIO_ACTIVE_LOW>;" at the i2c config. The vanilla 4.13 devicetree from my board shows something like "wake-gpios = <&pio 7 7 GPIO_ACTIVE_LOW>;". For what stands the first parameter `&pio`?
<apritzel>
zzeroo: that is the phandle of the pinctrl node
<icenowy[m]>
apritzel: mysteriously the H6 CCU do not have PIO clock
<icenowy[m]>
at least according to the user manual
<zzeroo>
apritzel: Is this optional or do I have to change this lines
<apritzel>
zzeroo: when it comes to phandle this editing in U-Boot becomes really tedious ...
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<zzeroo>
apritzel: No all I try to figure out is, why does my touchscreen under 4.6 and not under 4.13. This is because a wrong gpio or i2c config.
<apritzel>
icenowy[m]: that's just a clock gate anyway in the other SoCs?
<icenowy[m]>
yes
<icenowy[m]>
and in H6 now there's nothing
<zzeroo>
`edt_ft5x06 2-0038: Failed to request GPIO wake pin, error -22`
<icenowy[m]>
I checked BSP clk-sun50iw6.c and the pio clk is just a dummy one
<icenowy[m]>
all parameters are 0
<icenowy[m]>
or maybe it can be just set to APB1?
<icenowy[m]>
however usually the APB clocks shouldn't be exported
<apritzel>
icenowy[m]: I guess they just tied this gate to always on
<icenowy[m]>
yes
<apritzel>
icenowy[m]: so a dummy clock would be the answer then, as I guess our pinctrl binding requires a clock
<icenowy[m]>
as it nearly won't be gated at all
<willmore>
apritzel, I didn't mean to criticize PCI for that, it was never meant for that use. Sorry if I sounded like that. Since I had advocated a PCI like discovery, I was admitting that being like PCI wasn't enough for *this* use.
<icenowy[m]>
but we may remove it from the pinctrl binding
<apritzel>
icenowy[m]: rather make it optional for some drivers, I guess
<icenowy[m]>
oh I mean it
<apritzel>
icenowy[m]: as make a missing clock non fatal in probe()
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<icenowy[m]>
my fault
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<KotCzarny>
jernej: but that table doesnt mention which soc includes them
<KotCzarny>
not to mention it's not specific enough ie. video engine had few iterations
<jernej>
that's true
<jernej>
but it's a start
<KotCzarny>
yup
<jernej>
and may blocks are same through generations and some with minor changes
<jernej>
*many
<apritzel>
KotCzarny: jernej: one could base that on either DT compatible or look at what Linux drivers actually do for those different generations of IP
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<icenowy[m]>
finished an initial version of H6 CCU driver
<icenowy[m]>
oh converting user manual to code nearly drained out my brain
<KotCzarny>
poor you
<KotCzarny>
want the cookie?
<apritzel>
icenowy[m]: thanks a ton, indeed doesn't look like fun ...
<icenowy[m]>
let me finish the initial test, dry my hair and go sleep
<apritzel>
icenowy[m]: insert a "drop it somewhere" in between ;-)
<icenowy[m]>
ok let me drop a stash
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<wens>
icenowy[m]: you should probably just send out an initial support (platform, basic dtsi with cpu and uarts) series
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<icenowy[m]>
yes but won't be today
<icenowy[m]>
wens: should the "apb" clock of H6 pinctrl ignored or set to the apb1 clock?
<icenowy[m]>
the bus gate is removed from CCU (seems to be hardwired to open)
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<wens>
so you poked the register?
<apritzel>
wens: there does not seem to be a register ...
<wens>
apritzel: you mean the bus clock gate right?
<wens>
maybe it's just undocumented?
<icenowy[m]>
good night ;-)
<wens>
best to try it
<apritzel>
icenowy[m]: sleep well!
<apritzel>
wens: all the gate bits have been moved to new registers
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<apritzel>
and there is no one dealing with PIO or something
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<wens>
I see
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<apritzel>
for instance there is a "UART bus gating reset register", where bits 19:16 control the reset, and bits 3:0 control the clock gates
<icenowy[m]>
wens: in uart0-helloworld-sdboot I didn't enable the clock of PIO at all
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<icenowy[m]>
but PIO still works
<wens>
icenowy[m]: to be fair, I don't think we needed to enable the PIO bus gate in any of the socs
<apritzel>
did the BROM disable the PIO gate on older SoCs?
<wens>
the BROM would enable it as part of trying to find boot media
<wens>
or it was just on by default
<icenowy[m]>
oh I forgot it
<icenowy[m]>
A SoC without PIO is unfunctional
<icenowy[m]>
:-)
<silviop>
I'm try to port BSP driver to mainline i stuck in gpio_to_irq(config_info.int_number); i'm not use device tree for now so hw conf is embedded in driver i have port:PA03<6><default><default><default> in original fex
<silviop>
there is a conversion table ? (A33)
<icenowy[m]>
P.S. the xhci part of H6 seems to have a new dedicated PHY
<icenowy[m]>
but it can be expected
<wens>
silviop: A (convert to 0-based integer) * 32 + 3
<silviop>
A = 0 ?
<wens>
yes
<silviop>
= 0 * 32 + 6
<wens>
what's with the 6
<wens>
isn't your pin PA3?
<silviop>
yes
<wens>
so it would be 0 * 32 + 3
<silviop>
ok i put 3 :-)
<icenowy[m]>
I think I can get MMC to work tomorrow (it's quite easy ;-) )
<BenG83>
AXP805 seems to support companion battery management ICs
<icenowy[m]>
yes
<BenG83>
wonder if there is a reference design
<icenowy[m]>
I think it's based on AXP806
<BenG83>
just reading the datasheet, it can handle almost double the power of AXP806
<icenowy[m]>
A80 devices use a AXP809+AXP806 combo
<icenowy[m]>
P.S. Wink seems to confirm ATE is an AC200
<BenG83>
ATE?
<silviop>
IRQF_DISABLED could be removed without problems ?(is deprecated in mainline)
<apritzel>
BenG83: "A"udit "T"V "E"thernet
<apritzel>
"A"udio*
<KotCzarny>
o.O
<icenowy[m]>
Audio Codec, TVE, EPHY controller
<BenG83>
ah ok
<BenG83>
does H6 have a manegement core?
<icenowy[m]>
ar100?
<icenowy[m]>
yes
<BenG83>
ok
<apritzel>
BenG83: not even guessing this time about the meaning of ATE, it's spelled out in the manual
<wens>
icenowy[m]: beware of hidden /2 post divider (new timing mode, always) for MMC clocks
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<KotCzarny>
funny as it is nmap detected my opipc running 4.13.16 as OS details: Linux 3.11 - 3.14
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<apritzel>
smaeul: ah, interesting, didn't know
<apritzel>
I fixed CPU hotplug lately in my branch as well
<apritzel>
smaeul: and great to see that you have an I2C driver, I wanted to add this on the weekend
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<smaeul>
yeah, I developed this on opi pc2, then added a64 later once I got more hardware
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<apritzel>
smaeul: In my port I have a plat/allwinner/sun50i-{a64,h6,common} directory scheme
<apritzel>
since H6 and A64 have a completely different memory map, this seems to be the best approach, with different _def.h files for each
<apritzel>
smaeul: I2C, RSB and stuff would be in plat/allwinner/common/drivers then
<apritzel>
smaeul: and H5 and A64 can share a directory
<smaeul>
right
<smaeul>
apritzel: one thing to consider/build consensus on:
<smaeul>
my current project is writing an arisc firmware that implements scpi
<smaeul>
but that means there's not enough space in SRAM A2 for bot
<smaeul>
*both
<smaeul>
so where to move ATF?
<apritzel>
smaeul: just found your arisc port ;-)
<apritzel>
I was always thinking of using SRAM A1
<smaeul>
1) is it possible for u-boot spl to load something over itself
<apritzel>
SRAM C is probably of limits, because this is married to the DE
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<smaeul>
2) I don't think A1 is large enough -- only 32k
<apritzel>
1) yeah, that would be interesting, but solvable somehow
<smaeul>
I was never able to get ATF smaller than 52k because it has a bunch of page tables, and a page for locks
<apritzel>
2) mmh, is latest ATF so much bigger? The AW 1.0 port is only about 32K
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<DavidO_>
hey
<DavidO_>
i need help
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<DavidO_>
how can i add support for orange pi prime on buildroot?
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<apritzel>
smaeul: maybe we could start with loading ATF to SRAM A2, then relocate the *resident* part to A1
<apritzel>
smaeul: which may be smaller than the whole ATF
<smaeul>
apritzel: let me paste the map file
<apritzel>
smaeul: and the arisc could be loaded somewhere else first, then moved to A2 after ATF is out of the way
<KotCzarny>
isnt arisc able to use main memory too? slow but usable?
<smaeul>
apritzel: i guess? arisc can't be anywhere else though, because of the power domains
<smaeul>
KotCzarny: only when DRAM is on :)
<apritzel>
smaeul: if you have the arisc doing power management (via SCPI, for instance), ATF would not need all those RSB/I2C drivers
<smaeul>
apritzel: I found out that SRAM A1 is not accessible from ARISC at all
<DavidO_>
is buildroot not yet compitable with the orangepi prime?
<DavidO_>
i lost 3 weeks on this
<DavidO_>
or im just dumb
<apritzel>
smaeul: yeah, the arisc code would be loaded somewhere else first, then moved to A2 by ATF, after it's own relocation
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<smaeul>
apritzel: with -flto and -fno-common, and removing all of the power drivers, this is the map for my ATF http://sprunge.us/XJii, so 52k minimum
<smaeul>
is there a good reason not to put ATF in DRAM?
<smaeul>
other than that the TZASC doesn't work in non-secure mode