<TheSeven>
hmm... still messing with that SPI flash, and I have no idea what I'm missing
<TheSeven>
it just doesn't show up on linux, and I'm not quite enough of a device tree expert to figure out why ;)
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<pgreco>
Does anybody know if usb should be working on bpi-m2U (r40)?
<pgreco>
according to the status matrix it should be, but I can't get it to detect anything off usb
<BenG83>
everything enabled in your config?
<pgreco>
should be, I may be missing some "modprobe", but don't know which ones to test
<pgreco>
The same image (Fedora rawhide with kernel 4.15rc4) works ok on my bpi-m3 (a83t)
<BenG83>
anything missing in the dts?
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<pgreco>
BenG83, no, dts is the same on my config as in next-20171222
<pgreco>
and last commit is "enable usb"
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<pgreco>
icenowy[m] ^^
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<TheSeven>
gah...
<TheSeven>
if anyone ever runs into the same thing... turns out that CONFIG_MTD_SPI_NOR isn't what you need. it just unlocks CONFIG_MTD_M25P80 which handles all kinds of SPI flash, not just M25Pxx
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<montjoie>
KotCzarny: do not know, according to usermanual, it is PHY which do that part, and it is not documented
<KotCzarny>
oh, that might be interesting then
<KotCzarny>
ie. not having to write whole packet engine
<KotCzarny>
bad thing it's undocumented
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<KotCzarny>
montjoie: then again, how much code would it require (in ~lines) to write basic bare-metal driver that would only need to check for specific packets?
<KotCzarny>
The magic packet is a broadcast frame containing anywhere within its payload 6 bytes of all 255 (FF FF FF FF FF FF in hexadecimal), followed by sixteen repetitions of the target computer's 48-bit MAC address, for a total of 102 bytes.
<KotCzarny>
so basically just a data sniffer
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<DonkeyHotei>
are there any cheap boards that have a second uart already exposed in the dts with rts/cts?
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<DonkeyHotei>
there is no L in my nick, so i did not get pinged
<pgreco>
DonkeyHotei, sorry, typo...
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<icenowy[m]>
DonkeyHotei: you can modify the DT
<DonkeyHotei>
icenowy[m]: yeah, but not every board has the pins exposed
<DonkeyHotei>
and it looks like the m1 does not
<kevans91>
icenowy[m]: Hey, question... was there any status on verifying the rgmii-txid change for Pine64 that you had proposed?
<icenowy[m]>
kevans91: I nearly abandoned it
<icenowy[m]>
the Ethernet PHY maintainer required too much things that is beyond my knowledge
<icenowy[m]>
and I cannot get more info from Realtek
<kevans91>
icenowy[m]: =( I understand
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<DonkeyHotei>
looking at the dts for the nanopi m1+, the second uart in it looks like it's not actually exposed on the board, but two are that aren't in the dts
<DonkeyHotei>
weird
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<DonkeyHotei>
and the same situation with the bananapi m2+, but in reverse
<DonkeyHotei>
looks like wens was responsible for that one
<DonkeyHotei>
uart1 vs. uart3
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<kevans91>
icenowy[m]: Might not be ideal for what you're wanting, but can we at least get Pine64 folk to confirm that rgmii-txid is how the PHY needs to be configured and get the .dts change in? I might be able to get one of these in the hands of someone that can verify the register-writes if so
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<icenowy[m]>
kevans91: everyone can cherry-pick my patch if he/she think it propriate
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