Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> victhor: otg is bad, don't use it if you can
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<victhor> right, unfortunately it's my only option :<
<wens> there's no dma with otg
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<icenowy[m]> victhor: the OTG controller is just terrible on A33
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<victhor> that explains why it's so bad
<victhor> thanks
<icenowy[m]> I think the MUSB controller used by AW on OTG controller is so old
<anarsoul> is it possible to switch it to ehci like on a64?
<icenowy[m]> no
<icenowy[m]> this option is provided first at H3
<icenowy[m]> in fact I think the OHCI/EHCI on USB0 is just provided for working around bad MUSB
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<anarsoul> icenowy[m]: btw, do you have any idea why PLL_MIPI isn't working as parent for TCON0 clock on A64? PLL_VIDEO0_2X works fine
<icenowy[m]> P.S. I think DWC is much better than MUSB, but I don't think AW will purchase one new IP core when they have one that works
<icenowy[m]> no idea...
<anarsoul> icenowy[m]: DWC2 also sucks
<icenowy[m]> but I think I have met the same problem on A33
<wens> the LDO's aren't enabled
<icenowy[m]> oh I think A64 CCU driver didn't enable some bits in PLL_MIPI control register
<icenowy[m]> yes
<wens> anarsoul: compare pll-mipi definition in ccu-sun6i-a31.c vs ccu-sun50i-a64.c
<icenowy[m]> add &quot;| BIT(22) | BIT(23)&quot; to the .enable part of the pll_mipi_clk in ccu-sun50i-a64.c
<icenowy[m]> .enable= BIT(31) | BIT(22) | BIT(23),
<icenowy[m]> A64 CCU is developed too early that developers are still not aware of this problem at that time
<anarsoul> icenowy[m]: let me try it
<wens> icenowy[m]: why is your " (quote) &quot;
<icenowy[m]> just do not want to mix code with description
<icenowy[m]> oh... maybe I should use ` ` as it means code in markdown
<anarsoul> icenowy[m]: nope, it doesn't help.
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<wens> icenowy[m]: what I meant was it's getting escaped into html special character form
<wens> icenowy[m]: are you using a web client?
<victhor> the A33 reference manual says "support the embedded DMA" for the OTG controller, but that obviously doesn't work, given what I was told and additionally CPU usage is quite high when using that port
<wens> victhor: it's not supported
<victhor> this is annoying, when the documentation says the hardware supports something it can't do
<wens> the software supported isn't there, not the hardware
<wens> btw, the "embedded" DMA engine seems to be shit
<wens> vendors will pair it with an external system DMA engine
<victhor> oh I see now. thanks
<anarsoul> wens: is pll-mipi definition for a64 supposed to be the same as for a31?
<wens> supposedly, but the manual does have the bit definitions
<wens> look them up?
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<anarsoul> wens: ok
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<smaeul> wens: anyone with [m] after their nick is using the Matrix gateway
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<wens> oh
<aalm> what
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<montjoie> wens: after booted a recent kernel, I need to a real power off for network works again
<montjoie> so seems kernel related and not uboot related
<wens> mine seems quite well
<wens> have you checked your gmac clock / syscon register values?
<montjoie> not yet
<montjoie> additionnaly axp20x pinctrl crash on my last try
<montjoie> nullptr deref
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<montjoie> wens: it's not syscon since it get the default value
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<montjoie> wens: it's a clk problem "bus-emac 2 2 300000000 50000 0" <- bad
<montjoie> good = bus_emac 1 1 300000000 0 0
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<IgorPec> montjoie: you have a working dwmac on 4.14.y? I am trying to backport from 4.15.y but no luck so far
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<montjoie> IgorPec: which part (dt/code) you fail to backport ?
<IgorPec> dt - only one diff
<IgorPec> i ended up with platform 1c30000.ethernet eth0: Could not attach to PHY
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<IgorPec> i see someone has done something similar: https://irclog.whitequark.org/linux-sunxi/2017-12-12#;dwmac-sun8i
<IgorPec> but can't find that patch
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<montjoie> which diff ?
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<icenowy[m]> mripard: as we do not have reliable way to test maximum DRAM freq on H5, should we use veto policy on this?
<icenowy[m]> that means if anyone reports system instability fixed by DRAM downclock, we should downclock to a frequency that the problem disappears
<KotCzarny> icenowy: ssvb's original work used statistical analysis to set the reliable freq
<KotCzarny> http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit_.28automated_statistical_analysis.29
<icenowy[m]> it's based on a huge volume of data
<KotCzarny> yes, but remember that there might be faulty samples
<KotCzarny> and statistical analysis helps to set the reliable threshold
<KotCzarny> without going overboard
<KotCzarny> there is also a matter of ambient temp, emi, bad reports (ie. bad psu) etc
<icenowy[m]> in the OPi PC case the statistical analysis data is even lower than the last successful case
<icenowy[m]> so it's why I say &quot;fixed by DRAM downclock&quot;
<KotCzarny> what if it would came from someone who has bad psu/cables?
<icenowy[m]> then how can it be fixed by DRAM downclock?
<KotCzarny> lower dram clock -> just enough less power needed to make it work?
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<KotCzarny> one become sentient and crawled away
<KotCzarny> oops, wrong chan
<montjoie> IgorPec: why did you backport timer change ?
<IgorPec> i see, that's not needed
<IgorPec> well, i have to spent a day to sort out our patches. it's a big mess in any case
<montjoie> and it reduce heavily the patch
<IgorPec> thanks. i'll rework it later
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<BenG83> I have a problem to get GbE working on a SOPine, using 4.14.6-sunxi64
<BenG83> I tried both in baseboard and clusterboard
<BenG83> I get
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<BenG83> [ 1.782901] dwmac-sun8i 1c30000.ethernet: Cannot register the MDIO bus
<BenG83> [ 1.782910] dwmac-sun8i 1c30000.ethernet: stmmac_dvr_probe: MDIO bus (id: 0) registration failed
<BenG83> full log is here
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<montjoie> BenG83: could you paste the DT EMAC node ?
<BenG83> montjoie, yes give me a sec
<mripard_> icenowy[m]: we talked about that already
<mripard_> if the allwinner's stack run at the same memory settings without any hiccups, then no, we won't lower the memory frequency
<mripard_> because it's just putting blanket on the issue instead of fixing it
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<montjoie> BenG83: the MDIO node need the compatible
<montjoie> BenG83: compatible = "snps,dwmac-mdio";
<BenG83> ok
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<BenG83> [ 14.213366] dwmac-sun8i 1c30000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
<BenG83> that seems to do it, thanks
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<montjoie> wens: my problem comes with ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
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<TheSeven> does someone know what's the matter with u-boot and SPI flash (on H2+)?
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<TheSeven> are there any roadblocks here or is it just a matter of nobody caring enough about SPI flash to go ahead and implement it
<TheSeven> seems odd as apparently the SPL can read SPI flash at least?
<smaeul> you need to enable DM_SPI and DM_SPI_FLASH
<TheSeven> DM_SPI doesn't seem to unlock any driver that looks relevant to this hardware though
<smaeul> that's from Wizzup here
<TheSeven> ah thanks, that's what I was missing then...
<TheSeven> do you know why that hasn't landed upstream yet? seems like a rather straightforward thing
<smaeul> not sure if it's been tested on h5, but it should be a start
<smaeul> lack of interest? no idea
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<TheSeven> btw, just for reference, that doesn't compile cleanly anymore
<TheSeven> there's a line where int node = bus->of_offset; needs to be replaced with int node = bus->node.of_offset;
<TheSeven> and it has an undefined reference to dev_get_addr, looking into that...
<BenG83> TheSeven, I am trying to get SPI Flash working on A64 for SOPine atm
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<BenG83> TheSeven, Wizzup told me there was more or less a request for feedback on the mailinglist but not many replies
<BenG83> check yesterday's log
<beeble> BenG83: a64 aware spi driver is also available on the ml
<BenG83> ah thanks beeble
<beeble> but since it depends on dm patches never merged either you may have problems too
<BenG83> ok
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<TheSeven> hmm now I have a DT syntax error, wtf... never even touched that
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