<wolfspraul>
the other day lekernel said fpgas are mostly designed/optimized for synchronous designs
<wolfspraul>
I'm wondering what the underlying technical reasons are? What specifically makes them geared towards synchronous vs. asynchronous designs?
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<wpwrak>
perhaps the structure of the clock distribution ?
<wpwrak>
e.g., perhaps many things connect to the same clock ? (instead of letting you just use any random signal as clock)
<wpwrak>
Fallenou: wow. 1 k TLB entries. that's **!!!*HUGE*!!!**. 1k+1k may be the largest TLB in existence for a uniprocessor design :)
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<Fallenou>
(huge TLB) : yes but we don't have hardware page table walker, so tlb miss will be quite expensive (exception raised, then software lookup, TLB refill, and return from exception)
<Fallenou>
so we want to avoid spending all the cpu resources on TLB refilling :)
<Fallenou>
and we have BlockRAM resources, better use them ! ;)
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<wpwrak>
well, if you have block RAM to burn ... ;-)
<wpwrak>
the TLB size probably doesn't help all that much to improve performance. but let's see ...
<Fallenou>
wpwrak: anyway it's not hard coded, you can easily change the TLB size in the code
<Fallenou>
and all the rest of the code will adapt to it
<Fallenou>
index width, bit position etc
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<wpwrak>
great
<Fallenou>
wpwrak: that could be a marketing bullshit pitch line "we have a f*cking huge TLB"
<Fallenou>
bigger than Cortex A15
<Fallenou>
too bad our value is not in marketing BS :p
<wpwrak>
use of the lowest bit of a phys/virt address as TLB selector seems a bit hackish. but perhaps you often need to mix other bits in there anyway ?
<wpwrak>
"The M in M1 is for Monster" ;)
<Fallenou>
ahah
<Fallenou>
(but perhaps you often need to mix other bits in there anyway ?) <= what do you mean ?
* Fallenou
didn't get that
<wpwrak>
things like permission bits, when writing a TLB entry
<wpwrak>
i suppose they would also be encoded in the address, wouldn't they ?
<Fallenou>
yes
<Fallenou>
in the page offset
<Fallenou>
you have 12 free bits
<Fallenou>
err 11 free bits
<Fallenou>
because lowest bit is used to chose the TLB :)
<wpwrak>
so these registers are write-only ?
<wpwrak>
or do you get anything meaningful if you read them ?
<wpwrak>
i should actually ask this on the list :)
<Fallenou>
hehe that would allow someone else to benefit from the information
<Fallenou>
you cannot read back what you have written in TLBCTRL, TLBPADDR and TLBVADDR
<Fallenou>
the rcsr (read) gives you another kind of information
<Fallenou>
reading tlbpaddr and tlbvaddr gives you address of latest tlb miss
<Fallenou>
in my sample code, I read it in the miss handler
<wpwrak>
could this perhaps be connected to the problems you're experiencing ?
<Fallenou>
hum it's something else
<Fallenou>
it's about when wishbone says "error !"
<Fallenou>
I've seen a comment in the code about that
<Fallenou>
let me find it
<wpwrak>
ah, good. so you're not using that mechanism
<Fallenou>
no I'm not
<Fallenou>
it's for unaligned access or something like that
<wpwrak>
hmm. i wonder if this could cause trouble for linux. hopefully only in theory
<Fallenou>
well, we cannot forbid the user to try to do unaligned access
<Fallenou>
so we have to handle this correctly in the exception handler
<Fallenou>
unfortunatel
<Fallenou>
+y
<Fallenou>
maybe another upcoming surprise :)
<Fallenou>
wpwrak: for now I only added two exception vectors : DTLB_MISS and ITLB_MISS
<wpwrak>
i guess it all depends on just how much of a mess LM32 can leave behind in such a case
<Fallenou>
I don't know yet if I will share those too with the "page fault" (read/write/execute protection stuff)
<Fallenou>
or if I will add exception vector specific to protection fault
<wpwrak>
how would permission checks work ? e.g., if there's a write to an address that isn't in the TLB. would the TLB fault handler add the entry, return, and then, if there's a permission issue, you'd get another fault ?
<wpwrak>
you also get a pseudo-exception, which is the page fault (i.e., if a page isn't present). that would basically be a continuation of the TLB fault
<wpwrak>
in case we add a page table walker later, it would become an exception on its own and the TLB faults would disappear
<Fallenou>
wpwrak: I would say : 1°) TLB miss exception, TLB is refilled, access is replayed 2°) protection fault because the type of access violates the page right
<Fallenou>
so two exceptions
<Fallenou>
wpwrak: page table walker is really a mess to implement
<Fallenou>
it will touch a much broader part of the lm32 source code
<wpwrak>
two exceptions sounds good. checking permissions in software may be messy
<Fallenou>
I am trying to touch as little as possible the source code