<kristianpaul>
hum that migen re-use for just top and csr generation dont look bad
<kristianpaul>
just to get used to the pythonic way of writing the top "config file"
<kristianpaul>
:-)
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<xiangfu>
azonenberg, Hi
<azonenberg>
hi
<azonenberg>
whats up?
<xiangfu>
azonenberg, I try to make a tiny slx9 board for learn. the first thing I need to is: power-on the chip and make jtag detect the chip.
<azonenberg>
xiangfu: Sorry, cant talk tech now - it's 3AM and i'm getting ready to go to sleep
<xiangfu>
azonenberg, sure.
<azonenberg>
i'll be hanging out with $GF tomorrow but if you ping me in the early evening my time (EDT) i'll see what i can do
<xiangfu>
azonenberg, good night. thanks.
<xiangfu>
azonenberg, I learn base on your slx9-azonenberg-devboards , BTW. :-)
<azonenberg>
Glad to hear it's getting used
<azonenberg>
I assembled one of the boards and it works fine
<azonenberg>
will do the other two soon
<azonenberg>
The one mistake in the original design was that R8 (I think? the 10k pulldown on one of the mode pins) should have been 10 ohms, or any small value
<azonenberg>
i forgot the chip has an on-die pullup and you have to pull down strongly enough to override that
<azonenberg>
Not a layout change, just a BOM tweak
<xiangfu>
I read that. you rock and fast. I am working very hard try to catch up with you. :-D like make a board in one day.
<xiangfu>
I finished soldering my first QFP 144 by hand.
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<xiangfu>
azonenberg, one simple question. there are like 5 VCCINT/AUX/_O pins. for power-on the chip. I only needs connect one GND, one VCCINT, one VCCAUX and one VCC_O_2 is enough, right? no needs connect all them
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<Hawk777>
xiangfu: in most cases they will all be connected together inside the package, *but* you will have issues if you don't connect all of them because the inductance of the pins on the chip will be higher than expected so there can be more voltage drop during switching inside the chip
<Hawk777>
I believe you can safely leave out the VCCOs for I/O banks you're not using at all, though.
<xiangfu>
Hawk777, from the datesheet. if I understand right. I have to connect VCCO_2 for using jtag
<xiangfu>
Hawk777, thanks for reply
<Hawk777>
probably, if that's the I/O bank the JTAG pins ar ein
<Hawk777>
I use SLX9 myself in a project, but I haven't done JTAG and I've always just connected VCCINT to 1.2 and every single other power supply pin to 3.3
<xiangfu>
my side is ever simple. I just want make the jtag detect the chip correct. so I connect VCCINT to 1.2, VCCAUX to 2.5 and VCC_O_2 to 3.3.
<xiangfu>
then connect those 4 jtag pins.
<Hawk777>
that'll probably work
<xiangfu>
maybe I try to connect VCCAUX to 3.3? like you do?
<Hawk777>
did you try your idea and it didn't work?
<xiangfu>
now the pins are connected. when I run 'detect', I always get ' TDO seems to be stuck at 1'
<Hawk777>
ah, just a big breakout
<Hawk777>
hm
<Hawk777>
stuck at 1 is kind of weird
<Hawk777>
if it's not powered I would have expected stuck at 0
<Hawk777>
unless there JTAG host has a pull-up resistor or osmething
<Hawk777>
anyway I just use 3.3 VCCAUX because then I don't need a 2.5 V regulator on my board
<Hawk777>
"For configuration, Spartan-6 devices require power on the VCCO_2, VCCAUX, and VCCINT pins."
<Hawk777>
So there's your answer: none of the other I/O banks should be needed.
<Hawk777>
Maybe you want to try providing power to all the VCCAUX and VCCINT pins instead of just one of each?
<xiangfu>
Hawk777, I tried 3 of them. now. I connect all them ....
<xiangfu>
I must do something wrong. it still give 'stuck at 1'
<Hawk777>
do you have any way to look at the JTAG pins, maybe a scope?
<xiangfu>
I have a usb hantek scope. but I dont' have much experience on scope.
<Hawk777>
ah, well the idea would be just to look at the TDI, TDO, TMS, and TCK lines to see if there's any activity at all
<Hawk777>
also, that board you sent the photo of
<Hawk777>
did you make that yourself, or buy it?
<Hawk777>
(soldering the FPGA)
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<xiangfu>
I soldering them by myself. I bought this premake PCB.
<Hawk777>
ok
<Hawk777>
because maybe there's a solder bridge between two pins and one of them is a JTAG pin?
<Hawk777>
that would explain a stuck pin
<xiangfu>
I check the 4 jtag pins many time. I am sure they are good.
<Hawk777>
ok
<Hawk777>
Ah, it's not something about crossing wires is it? Haven't used JTAG so I don't know, but maybe TDI on the FPGA has to go to TDO on the host and vice versa or something like that?
<Hawk777>
Or maybe if you did that, it's not supposed to?
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<xiangfu>
Hawk777, crossing wires. no. I have double check them.
<Hawk777>
ok
<xiangfu>
Hawk777, maybe I try to soldering another board.
<Hawk777>
you could
<Hawk777>
maybe the FPGA was damaged at some point
<xiangfu>
not sure if I broken this chip when I soldering this one.
<xiangfu>
Hawk777, yes. soldering another one in next hour.
<Hawk777>
heh, yeah :/
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<azonenberg>
xiangfu: you have to connect all of the vccint and vccaux for the chip to work reliably
<azonenberg>
vcco_2 is needed for jtag
<azonenberg>
check the datasheet, it may be possible to leave off vcco for banks you arent using
<azonenberg>
BUT
<azonenberg>
you should probably ground it rather than leaving it floating
<azonenberg>
which wont be any harder to route, probably, than hooking it up properly
<xiangfu>
azonenberg, thanks.
<sb0>
iirc the FPGA only starts to configure after all VCCO's have reached some level
<azonenberg>
I've always hooked them all up
<azonenberg>
its doable on 2 layers
<azonenberg>
for a tq144
<xiangfu>
all VCCO's?
<azonenberg>
yes
<xiangfu>
ok. I will try connect all VCCO
<azonenberg>
look at my board
<azonenberg>
i had two concentric rings on one layer and a plane on the other
<azonenberg>
i even got in nice decoupling
<azonenberg>
while routing about half of the IOs to headers and useful stuff
<azonenberg>
i could have routed the other IOs too but not without making the board larger
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<Fallenou>
rejon let him complain (about price increase) :)
<Fallenou>
and maybe he is not wrong, maybe a prince increase communicate can somehow have positive outputs ^^
<Fallenou>
I don't know how :p
<Fallenou>
but sometime relationship between price and sells is tricky
<Fallenou>
that may send a signal to some company which could start paying attention to Milkymist / Ben
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<mwalle>
Fallenou: for debug purposes, eg for the debug monitor
<mwalle>
Fallenou: i guess it isnt hard to read back the value of the internal RAM for a given VADDR
<mwalle>
Fallenou: wpwrak: do we need the protection bits for both user and kernel access?
<Fallenou>
well it may need to use a dual ported blockram
<Fallenou>
or it may need to disable tlb
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<mwalle>
Fallenou: isnt it as easy as return dtlb_read_data on read on PADDR?
<Fallenou>
well you need to feed "address" signal of blockram with your VADDR
<Fallenou>
in this precise condition (rcsr on PADDR)
<mwalle>
Fallenou: yeah, you write VADDR and read PADDR
<Fallenou>
while you are fetching other instructions
<Fallenou>
which means you need in parallel to have address_a in address signal of blockram
<mwalle>
assume MMU is turned of, because its only for debugging ;)
<Fallenou>
to lookup address_f (fetch)
<Fallenou>
if mmu is turned off, then it's easier of course :)
<mwalle>
mh ok, i see, the problem is that the tlb is used by the instruction unit and the cache while a user may try to access it
<mwalle>
Fallenou: well in that case, we may drop this ;
<mwalle>
its just a nice to have
<mwalle>
if you put a mux in before the dtlb_data_read_address, there may be other side effects if you switch the mmu on and off, i guess
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<Fallenou>
mwalle: that's what I fear indeed
<Fallenou>
maybe I will try when tlb will be rock solid stable
<Fallenou>
but for now, even with the very limited feature set I have right now, it still has bugs
<Fallenou>
so first, I improve stability :)
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