<GitHub126>
[migen/master] doc: actor network - Sebastien Bourdeauducq
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<azonenberg>
lekernel: i've read a bunch of appnotes, let me see that one
<azonenberg>
Well they very strongly recommend 6-layer (3S3P or 4S2P) stackups in most cases lol
<azonenberg>
so i'm already violating most of their guidelines by using 2 layers :p
<azonenberg>
sorry, 2 signal layers
<azonenberg>
2S2P on 4 layers
<azonenberg>
oh, and lack of controlled impedance
<azonenberg>
But i dont think that at 240 MT/s (120 MHz) that wil.l matter quite as much as 400 MT/s 200 MHz
<wpwrak>
a true luddite would use a single-sided FR2 board and mount the chips on DIP adapters
<azonenberg>
wpwrak: not for DDR memory lol
<azonenberg>
I was getting ~160mV peak to peak ripple on my SSTL Vref
<wpwrak>
did i mention running everything at 5 V ? ;-)
<azonenberg>
put 10nF across the output of the regulator (right by the reg, the RAM is about 1/2" away and the FPGA 1-2" away) and ripple went down but i still am getting a lot of bit corruption
<azonenberg>
once i'm fully awake i'm gonna put another 10nF across the other side of the Vref bus near the FPGA
<Fallenou>
put 10nF everywhere :p
<azonenberg>
i dont want to put the board under the knife until i'm awake
<azonenberg>
lol
<azonenberg>
i also dont know for sure if Vref is the only problem
<wpwrak>
yeah. the more caps, the merrier
<azonenberg>
i know i was getting crosstalk on Vref from DQ1
<Fallenou>
and make sure to put the capacitances very near the DDR chip pins
<azonenberg>
its an 8 bit data bus and i'm testing with 0x00FF00FF since thats worst case crosstalk from DQ* to other signals and worst-case SSO
<wpwrak>
is that the only ground layer ?
<azonenberg>
No
<wpwrak>
good :)
<azonenberg>
Stackup is signal and ground fill on top
<azonenberg>
then a power plane broken in a few spots (mostly under the DDR chip and between it and the FPGA) for extra signal routing
<azonenberg>
then solid ground broken only by via antipads
<azonenberg>
then the green layer, signal with ground fill
<wpwrak>
perfect
<azonenberg>
all main components are on top copper except for the INA226 current shunt monitors (under the power supply area at top left)
<azonenberg>
most small bypass caps are on the bottom but all of the big tantalum/ceramic tank caps are on top
<azonenberg>
when i write 0x00FF00FF to the bus with no capacitance on Vref, it read back as 00FB00FF (I don't know whether the write or read was corrupted, that's still being investigated)
<azonenberg>
My oscilloscope is 1Gsa/s with 100 MHz bandwidth so DDR at 120 MHz/240 MT/s is a little fast