lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<kristianpaul> wee
<kristianpaul> package for urjtag seems to work on F17 :D
<kristianpaul> at least for BIOS flashing.. lets try soemthing bigger and wipeout flash too
<wolfspraul> my god
<wolfspraul> what should we do?
<wolfspraul> distribute some valium among community members to avoid over-excitement?
* kristianpaul hide
<kristianpaul> s
<kristianpaul> no need for valium, i just took a nap :)
<kristianpaul> about urjtag, well, one the less thing i have to compile by hand also get more value /to my self/ to my FEL installation :)
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<GitHub44> [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/913232ef43982aff8c9529ad116fbfe91ef17268
<GitHub44> [board-m1/master] Power_Tree.sch: added currents - Adam Wang
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<lekernel> azonenberg: have you read this? http://download.micron.com/pdf/technotes/DDR/tn4614.pdf
<lekernel> there are a couple of pages on vref
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<GitHub78> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/920aa5dc60c0cccd706a51f480a70c845a58b4bf
<GitHub78> [migen/master] actorlib: merge composer into ala + derive ComposableSource from ActorNode - Sebastien Bourdeauducq
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<GitHub126> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fa5a9915c3eaf5235411e3b0ea5f912f1c731ef7
<GitHub126> [migen/master] doc: actor network - Sebastien Bourdeauducq
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<azonenberg> lekernel: i've read a bunch of appnotes, let me see that one
<azonenberg> Well they very strongly recommend 6-layer (3S3P or 4S2P) stackups in most cases lol
<azonenberg> so i'm already violating most of their guidelines by using 2 layers :p
<azonenberg> sorry, 2 signal layers
<azonenberg> 2S2P on 4 layers
<azonenberg> oh, and lack of controlled impedance
<azonenberg> But i dont think that at 240 MT/s (120 MHz) that wil.l matter quite as much as 400 MT/s 200 MHz
<wpwrak> a true luddite would use a single-sided FR2 board and mount the chips on DIP adapters
<azonenberg> wpwrak: not for DDR memory lol
<azonenberg> I was getting ~160mV peak to peak ripple on my SSTL Vref
<wpwrak> did i mention running everything at 5 V ? ;-)
<azonenberg> put 10nF across the output of the regulator (right by the reg, the RAM is about 1/2" away and the FPGA 1-2" away) and ripple went down but i still am getting a lot of bit corruption
<azonenberg> once i'm fully awake i'm gonna put another 10nF across the other side of the Vref bus near the FPGA
<Fallenou> put 10nF everywhere :p
<azonenberg> i dont want to put the board under the knife until i'm awake
<azonenberg> lol
<azonenberg> i also dont know for sure if Vref is the only problem
<wpwrak> yeah. the more caps, the merrier
<azonenberg> i know i was getting crosstalk on Vref from DQ1
<Fallenou> and make sure to put the capacitances very near the DDR chip pins
<azonenberg> they're routed worryingly close
<azonenberg> Fallenou: http://i.imgur.com/tEL3p.png
<azonenberg> this is top and bottom copper only with ground fills hidden
<azonenberg> LP2995 reg outputs two independent 1.25V lines for Vtt and Vref (the SOIC8 at top left near the big tant caps)
<azonenberg> Vref runs on bottom layer (green) down the left side of the board
<azonenberg> under the DDR chip, then in to the FPGA at the bottom left
<wpwrak> kicad .. nice. did you route manually or with freeroute ?
<azonenberg> this area here http://i.imgur.com/9yJYe.png is where i think noise is getting in
<azonenberg> all manual
<azonenberg> http://i.imgur.com/vhcBU.png shows that there's ground between the Vref trace and all other signal routing
<azonenberg> this is the full bottom layer including ground fills
<azonenberg> Vref is the long snaky trace on the left
<azonenberg> http://i.imgur.com/q7Jls.jpg is the assembled board (not that that will tell you much)
<azonenberg> its an 8 bit data bus and i'm testing with 0x00FF00FF since thats worst case crosstalk from DQ* to other signals and worst-case SSO
<wpwrak> is that the only ground layer ?
<azonenberg> No
<wpwrak> good :)
<azonenberg> Stackup is signal and ground fill on top
<azonenberg> then a power plane broken in a few spots (mostly under the DDR chip and between it and the FPGA) for extra signal routing
<azonenberg> then solid ground broken only by via antipads
<azonenberg> then the green layer, signal with ground fill
<wpwrak> perfect
<azonenberg> all main components are on top copper except for the INA226 current shunt monitors (under the power supply area at top left)
<azonenberg> most small bypass caps are on the bottom but all of the big tantalum/ceramic tank caps are on top
<azonenberg> when i write 0x00FF00FF to the bus with no capacitance on Vref, it read back as 00FB00FF (I don't know whether the write or read was corrupted, that's still being investigated)
<azonenberg> My oscilloscope is 1Gsa/s with 100 MHz bandwidth so DDR at 120 MHz/240 MT/s is a little fast
<azonenberg> http://imgur.com/a/HC7Cf#4 shows Vtt Vref DQ0 left to right
<azonenberg> and bus idle and active top to bottom
<azonenberg> when i put the capacitance on, Vref ripple dropped by a lot but the test data read as 00F800FF (even worse!)
<azonenberg> the wrong values are consistent across all tests i've run so far
<azonenberg> i need to get time on a faster scope...
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<wpwrak> does any significant time pass between write and read ?
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<kristianpaul> about crosstalk, is not LVDS good enought those days to implement serial ram memories for < 100Mhz range?
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<wpwrak> if you can afford the pin count ...
<wpwrak> ah, you said serial
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<lekernel> well, if you see behaviour changes when adding decoupling... you definitely have power integrity issues
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