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<lekernel>
Fallenou: hmm, we should move the mmu stuff to -ng I think.
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<Fallenou>
you mean I should rewrite it in python using migen framework ?
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<Fallenou>
or that I should commit mmu stuff in milkymist-ng/verilog/lm32 ?
<lekernel>
no no, the mmu stays in verilog
<lekernel>
I mean, just integrate it in the -ng code base (which shouldn't be difficult)
<lekernel>
I'll create a mmu branch and do it for you... will be the occasion for some testing/review
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<Fallenou>
Ok fine :)
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<Fallenou>
I need to add a few `ifdef CFG_MMU_ENABLED at a few places
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<Fallenou>
11:01 < Fallenou> Ok fine :)
<Fallenou>
and refactor a little bit the code
lekernel_ is now known as lekernel
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<Fallenou>
lekernel: the recent ITLB commits have made previous dtlb tests obsolete. They don't willingly activate ITLB, but at the return of the first "DTLB miss" it enables both ITLB and DTLB. And then a storm of endless ITLB misses :)
<Fallenou>
I will need to fix "detest" and "dtlbtest"
<Fallenou>
ITLB stuff is only on the "simulation project" for now
<Fallenou>
so dtlb tests should still be OK in milkymist-mmu repo
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* Fallenou
is putting `ifdef CFG_MMU_ENABLED everywhere
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<Fallenou>
lekernel: what's best to initialize regs, reg NAME = VALUE; or doing a if (rst_i) NAME <= VALUE; in the driving always @(posedge clk_i) ?
<Fallenou>
the second one uses less logic ?
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<Fallenou>
or can go to ASIC ? or something like that ?
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<kristianpaul>
no name = value;
<kristianpaul>
you need do that on reset
<kristianpaul>
name = value; <- i wonder hoe get sinthesized on asic :-)
<Fallenou>
OK that's what I thought
<Fallenou>
thanks
<kristianpaul>
perhpas in migen this reset logi is done automatically by reg = value; ^_^
<kristianpaul>
logic*
<larsc>
yea, another annoyance. I want a language which has native support for clockdomains and reset values and instantiates whatever is best for my target architecture
<larsc>
(and where it is an error to pass a signal from one clock domain to antother without proper synchronization)
<kristianpaul>
he :)
<kristianpaul>
A SoC description language... ?
<larsc>
a proper highlevel hdl language
<larsc>
uhm
<larsc>
s/ language//
<kristianpaul>
yup
<kristianpaul>
perhaps is not a language it self, just lack of more depth verification from the tools
<kristianpaul>
where are the lints tools..
<Fallenou>
maybe just do a few tools of static/dynamic analysis :)
<Fallenou>
coverity / cococinel etc
<larsc>
i want a proper language. development in vhdl/verilog is like writing for example sw in asm instead of C
<Fallenou>
coccinelle*
<Fallenou>
maybe migen can reach the level of feature/maturity you are searching for eventually :)
<kristianpaul>
ah xst have a -cross_clock_analysis
<larsc>
maybe
<kristianpaul>
but no worth get too much used to it perhaps
<kristianpaul>
Fallenou: indeed
<larsc>
unfortunately migen ist a AST generator and not a language
<kristianpaul>
can you make a equivalent problem like CDC but in C?
<kristianpaul>
and how the language specificaion aid/helps to solve it?
<kristianpaul>
cause i see more like a lack of integration of tools in the development workflow
<kristianpaul>
there is a flow indeed, but you still need to get details of every step to know when something got wrong
<kristianpaul>
larsc: or fpga still a very limited resource device
<kristianpaul>
just like when you use asm because cant affort allocate memory for C
<larsc>
i'm quite convinced that you waste more resources by writing suboptimal hdl code
<larsc>
just as most modern c compilers will write way more effective asm code than a human does
<Fallenou>
gn8 !
<lekernel>
language (eg CAL) will come... but for some stuff you need HDL
<lekernel>
migen already takes care of reset values btw
<lekernel>
Fallenou: and yes, use if(rst_i)
<lekernel>
reg xx = value has a (different) meaning on FPGA (register is initialized during bitstream load) but cannot be implemented on asic at all