<azonenberg>
so far i've just published my existing libraries (needed to do that anyway and this was a good excuse) as well as creating a skeleton schematic with a usb UART and some linear reg
<azonenberg>
i should have the sch done in an hour or so
<wolfspraul>
maybe we can mix and match a little with the milkymist kicad stuff, don't know
<wolfspraul>
at least on the library or style level, we see
<azonenberg>
ok
<azonenberg>
I'm releasing my board under BSD license btw
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<azonenberg>
with a comment added in the LICENSE file to make it clear that "binary form" includes physical PCBs, gerbers, masks, or anything other than native CAD formats
<wolfspraul>
sure
<wolfspraul>
if you would ask 10 different people what that meant you'd get 10 different answers :-)
<wolfspraul>
and a few more from the same people the next day...
<azonenberg>
"The two categories combined are intended to encompass all possible uses of these designs." leaves little room for misunderstanding, i think
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<wpwrak>
i wonder if there's a practical difference between 3-clause BSD and public domain ...
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<azonenberg>
wpwrak: there is, they have to acknowledge your work
<azonenberg>
and then there's the "use at your own risk" clause which never hurts
<azonenberg>
But other than the acknowledgement requirement, not really
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<wpwrak>
yeah, but i wonder if the acknowledgement has ever been actively enforced
<wpwrak>
and simply claiming somebody else's work probably conflicts with more general rights anyway. so that license may give you very little in practical terms.
<azonenberg>
wpwrak: yeah
<azonenberg>
But it's widely used and imposes virtually no restrictions that would result in someone choosing not to use it
<azonenberg>
i included a few optional components (FT232, GPIO header, flash) that can be left off if you want a simpler/cheaper design
<azonenberg>
the area cost is near zero
<azonenberg>
device is bus powered (mini USB)
<azonenberg>
i'm going to add a ground clip for a scope plus a bunch of probe pads once i do rough-draft layout
<wpwrak>
azonenberg: i think the idea is to have a two board design: one board with just the FPGA (which wolfgang expects to destroy with his experiments) and another board with the more permanent components (power and such)
<azonenberg>
wpwrak: well i want to be able to use the board too
<azonenberg>
so i figure i'll just put on all the stuff
<azonenberg>
then document which parts can be left off
<wpwrak>
hehe :)
<azonenberg>
and i cnat imagine any failure mode that would destroy the rest of the board
<azonenberg>
reworking the chip is a matter of hot air and 5 minutes
<wpwrak>
if all is on the same board, you'd have to rework the fpga to swap it
<azonenberg>
wpwrak: the component count is minimal though
<azonenberg>
its just decoupling caps
<azonenberg>
which have to be on the fpga board itself
<wpwrak>
if it's two boards, you just toss the dead one and put in the new one
<wpwrak>
no regulators ?
<azonenberg>
the support stuff is literally three vregs and a jtag port
<azonenberg>
plus peripherals you can leave off (clock crystal, some LEDs, reset button, SPI flash)
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<azonenberg>
and you'd have to solder the new fpga to a new board anyway
<azonenberg>
Taking an old one off with hot air is the work of 15 seconds
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<azonenberg>
wolfspraul: it looks like it'll be around 4 in^2 btw
<azonenberg>
Trying to shrink but not sure how much i can do
<azonenberg>
the fpga itself is like a square inch by itself and i need room around it for routing lol
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<lekernel>
I was wondering how many DDR3 chips you can hook up to a artix-7 before hitting some limits...
<lekernel>
xilinx motto: "when it gets complex, obscurity helps". early FPGAs had detailed timing models in the datasheets... and now "just use our timing analyzer software"
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<wolfspraul>
is the work finished? I mean the files in github? or you plan more?
<azonenberg>
wolfspraul: it's on google code
<wolfspraul>
if finished I will take a closer look. thanks a lot! I guess you will make some for verification, maybe I do the same here, need to go over the design first.
<wolfspraul>
this is very helpful
<azonenberg>
i've committed that version
<wolfspraul>
yes but do you think you are done for now?
<azonenberg>
the tinyurl goes straight to the SVN url for checking out the board files
<azonenberg>
and i am going to make one more verification pass
<wolfspraul>
ok
<azonenberg>
then send a run of 3 out to batch fab
<azonenberg>
lead time for fab+assembly+test will be around a month
<wolfspraul>
let me know when you think it's at a stable state, I guess that's soon or now
<wolfspraul>
bbiab
<azonenberg>
I'd appreciate a peer review before sending it out to fab
<azonenberg>
on the version in the repo
<wolfspraul>
excellent stuff, thanks a lot!
<wolfspraul>
yes
<azonenberg>
Just as a quick overview of what's on there - 3.3, 2.5, 1.2V regulators
<azonenberg>
mini USB port for power plus optional FT232RQ usb-uart
<wolfspraul>
have to run out, back in 20
<azonenberg>
Ok
<azonenberg>
It also has eight LEDs, a reset switch (which needs a "RESET" label still), a 5x7mm CMOS oscillator, a W25Q80BV flash chip or similar, a 20-pin FFC connector for GPIO (same pinout as all of my other boards), the usual 2x7mm JTAG header
<azonenberg>
as well as 10-pin FFC, which is my experimental nonstandard low-profile JTAG solution (much smaller than the normal Molex connector)
<azonenberg>
i left the standard one on there too both as a backup and for easy interoperability
<azonenberg>
Grounded 4-40 mounting holes in each corner, inset 2mm from the edges of the PCB
<azonenberg>
i'm going to draw up a formal BOM including digikey part numbers for all components
<kristianpaul>
nice looking board azonenberg !!
<azonenberg>
kristianpaul: ty
<azonenberg>
it's intended as a fairly minimalistic spartan6 platform
<azonenberg>
drawing up a BOM workup now to find the per-unit cost
<azonenberg>
most of the components on there can be left off to cut costs if you dont need them
<kristianpaul>
you already made it or just planning right now? or just ordering parts?
<azonenberg>
Just finished the layout like 15 mins ago
<kristianpaul>
:-)
<azonenberg>
And i have all the parts except the FPGA in my inventory already
<azonenberg>
while i do have spartan6 in inventory now they're all FT256 package
<azonenberg>
so i'm gonna have to order some tqfp ones
* kristianpaul
runs to take the bus
<wolfspraul>
can the chip operate with less voltages, say only 1.2V?
<wolfspraul>
the ios will be 1.2 too then, I guess. if it works at all?
<wolfspraul>
can it generate a clock without the oscillator?
<azonenberg>
wolfspraul: unless you want to use ring oscillators (unstable and uncontrolled frequency) you'll need the osc
<azonenberg>
you need 1.2 for the core and 2.5 or 3.3 for vccaux (configuration, PLLs, and a few other things)
<azonenberg>
plus vccio
<azonenberg>
the osc i specified is a 3.3v part
<azonenberg>
so you'd need all 3
<azonenberg>
i suppose you could remove the 2.5V reg and solder a wire from the 2.5V rail to the 3.3
<azonenberg>
the chip can run at 3.3 on vccaux
<azonenberg>
but for saving 50 cents idk if it's worth it
<wolfspraul>
how unstable is a clock generated inside the fpga?
<wolfspraul>
actually I think the fpga can run on the jtag clock as well
<azonenberg>
you might be able to route it off CCLK i suppose
<azonenberg>
In any case i'm documenting the optional parts
<azonenberg>
in the BOM
<wolfspraul>
what is cclk and where does it come from?
<wolfspraul>
I ran past it a few times but still haven't understood the whole clock regime :-)
<azonenberg>
sorry, cclk isnt it
<azonenberg>
tck
<azonenberg>
typo
<azonenberg>
cclk is the clock the fpga supplies to an external SPI flash chip during boot
<wolfspraul>
where does it come from?
<azonenberg>
there's an oscillator on the fpga but to my knowledge it's not exposed onto the routing fabric
<wolfspraul>
maybe you can just leave that running for regular operation?
<wolfspraul>
cclk = configuration clock
<azonenberg>
i dont think its possible to
<azonenberg>
i think the configuration state machine shuts it off
<azonenberg>
Let me rephrase that
<azonenberg>
i am not aware of a documented and vendor-supported means of doing that
<wolfspraul>
ok
<azonenberg>
The decoupling network is probably overkill unless you're doing high speed stuff but it's basically right off their reference designs
<azonenberg>
for the LX9
<azonenberg>
so i'm going to let sleeping dogs lie
<Hawk777>
wolfspraul: if you're talking about Spartan 6 series, see page 63 in the Configuration datasheet; the STARTUP_SPARTAN6 primitive *does* provide access to the nominally-50 MHz (±50%) configuration clock
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<Hawk777>
probably something similar for other families
<azonenberg>
Hawk777: ooh
<azonenberg>
very interesting
<wolfspraul>
nice, thanks!
<azonenberg>
So highly variable, probably on-chip RC, but it is exposed
<Hawk777>
yep!
<Hawk777>
(never used it for anything myself so YMMV, but have fun)
<wolfspraul>
but I think I could even use the jtag clock as well
<azonenberg>
Not sure if it stops when the TAP isn't being probed
<azonenberg>
if you just plug the cable into a circuit does it start clocking it?
<azonenberg>
or is it only during a scan operation
<wolfspraul>
good question, don't know
<azonenberg>
from what i know of the jtag state machine, it has to not clock during some parts of the process