<azonenberg>
wolfspraul: just committed a final BOm
<wolfspraul>
you are fast
<azonenberg>
$55.81 including PCB and all optional components
<wolfspraul>
I need to get my morning coffee
<azonenberg>
before bulk discount
<azonenberg>
iow, assuming you pay 17 cents for every single decoupling cap
<azonenberg>
$40.40 of that is the required stuff, the rest is optional accessories
<azonenberg>
Whoops, forgot to tab-to-space
<azonenberg>
fixed
<azonenberg>
wolfspraul: let me know when you've had a chance to look over the design in some detail
<azonenberg>
i'm probably going to add an oscilloscope ground clip and a couple of probe pads with silkscreened labels on interesting signals
<azonenberg>
but other than that it's finished
<wolfspraul>
I'm super focused on fpgatools hacking right now, but I will ask Adam whether he has some time to review the board
<azonenberg>
Ok, let me phrase this a little differently
<wolfspraul>
or when I need a little rest from coding, I will peek over it too, of course
<azonenberg>
I'm going to send the design out for first-run prototype fab tonight or tomorrow so any comments received after that point will have to wait for rev 0.2
<wolfspraul>
understood
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<lekernel>
funny, they had to trash their repository 3 months ago and restart from scratch. this reminds me of the times when milkymist was still using svn...
<wpwrak>
hmm, absolute libray name paths
<Jia>
2012-06-29 Nick Clifton <nickc@redhat.com> config/lm32/lm32.c (lm32_compute_frame_size): Fix typo.
<Jia>
it just a typo... ???
<lekernel>
"!current_function_is_leaf" turning into "crtl->is_leaf!" does look like it, yes
<wpwrak>
(at least) one unannotated component (P?). ERC passes after auto-annotation.
<wpwrak>
quite large series resistors for the LEDs (470 Ohm). that's about 2-3 mA
<wpwrak>
azonenberg: why is SPI_SCK on a voltage divider ? (R4/R5)
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<azonenberg>
wpwrak: did i not commit after annotating it?
<azonenberg>
and these are indicator LEDs, you dont need a lot of current
<azonenberg>
i run 470 on most of mine and it works well
<azonenberg>
re the divider, that's the recommended termination from the datasheet
<azonenberg>
UG380 page 52
<azonenberg>
2*Z0 from SCK to Vdd and Vss
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<Jia>
lekernel: but I can not build lm32-gcc still, can you?
<Jia>
it didn't fix the bug, I think.
<wpwrak>
pag 52 ? don't see it mentioned. if it's in a drawing, my page 52 has "Figure 2-21: Spartan-6 FPGA BPI Configuration Waveforms"
<azonenberg>
Board Layout for Configuration Clock (CCLK)
<azonenberg>
which doc version do you have? i'm reading v2.3
<wpwrak>
v2.4 :)
<lekernel>
Jia: didn't try... I have only been using clang+llvm+binutils lately
<Jia>
lekernel: cool
<wpwrak>
(CCLK termination) interesting.
<azonenberg>
wpwrak: yeah, i didnt do that on any of my past boards
<azonenberg>
the fpga booted fine
<azonenberg>
but i noticed significant overshoot on the scope
<lekernel>
we have it on the M1 (I remember that little mess), but I think it would work without
<lekernel>
it's not mentioned in all documentation versions (iirc)
<azonenberg>
i also noticed that the flash chip, rated for ~80 MHz operation, could only be used by user designs up to around 40
<azonenberg>
i was using on-chip termination for all of the data from me to the flash
<azonenberg>
i think that MISO needs termination too
<azonenberg>
i think i'm going to put a pad on there and i can always put a 0-ohm if it turns out to be unnecessary
<azonenberg>
that's the bug in my memory controller
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<azonenberg>
read is issued after a write but occurs before
<azonenberg>
so you end up reading what was there before the write happened
<lekernel>
beware, DRAMs also need a bus turnaround time and a write recovery time when switching from write to read ...
<azonenberg>
lekernel: the controller handles that fine
<azonenberg>
i've tested
<azonenberg>
this is a bug in the glue that goes from my SoC's internal bus to the MCB
<azonenberg>
i intend to explore replacing this module and the mcb with something else later
<azonenberg>
the wrapper is intended to make that easy should i choose to do so
<azonenberg>
in any case the sun is coming up so i'm off to get some sleep
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<wpwrak>
you may want to change the paths in *.pro
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<wpwrak>
basically sed s|/nfs/home/azonenberg/Documents/local/Electronics/kicad-|../../|
<wpwrak>
the unannotated components are the mounting holes
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<azonenberg>
wpwrak: interesting, they're P3-6 in my design
<azonenberg>
guess i never committed that version
<azonenberg>
will do that after i do a final review of the design for things like power trace widths etc
<azonenberg>
and i had it set to absolute paths? Good catch
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<wpwrak>
azonenberg: hmm, you could shrink the OHW logo and bring some I/Os out on a 100 mil header. easier for debugging (scope probes and such) than the small stuff
<wpwrak>
C19 is not very rework-friendly
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<wpwrak>
azonenberg: is the bead really enough to make bead+220 uF silo behave like the 44 R+10 uF usb 2.0 allows ? (page 177, section 7.2.4.1)
<lekernel>
sounds we can easily combine 2x 16-bit chips to make it look (almost) like a 32-bit chip and still it won't require write leveling
<lekernel>
(of course, this now requires BGA soldering on both sides of the PCB)
<lekernel>
so, with 4 of those combinations (which sounds feasible) and a artix-7, we have 140Gbps peak bandwidth, if it can take the SSO
<wpwrak>
SSO ?
<lekernel>
simultaneously switching outputs
<wpwrak>
ah ! one of those "new" parameters
<lekernel>
it causes ground bounce and power drops
<lekernel>
no, it's not new
<lekernel>
it's just that with so many I/Os that have to use the fastest slew rates (which causes the worst problems), we have to be careful
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<wpwrak>
(new) yeah. it's just the sort of things i never saw before looking at the FPGA data sheets. of course, the underlying physics have been around for a bit :)
<Thihi>
Some billions of years ;p
<wpwrak>
yeah. the part still left to dispute is in the range of split-seconds rather than years :)
<Thihi>
A split second sounds so fast. We could talk about trillions of planck time units to get a nice big number.
<GitHub21>
[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/iLsCVg
<GitHub21>
[milkymist-ng/master] framebuffer: chop memory words - Sebastien Bourdeauducq
<GitHub29>
[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/g8onuQ
<GitHub29>
[milkymist-ng/master] framebuffer: VTG and FIFO skeleton - Sebastien Bourdeauducq
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<hellekin>
hello radical techies :)
* larsc
throws a cobblestone at hellekin
<hellekin>
aie
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<azonenberg>
wpwrak: i will definitely be adding some more headers
<azonenberg>
re the cap, good point
<wpwrak>
kewl
<azonenberg>
i'm used to running off wallwarts
<azonenberg>
and putting a ton of capacitance on
<azonenberg>
i probably dont need nearly that much before the reg if its running off a nice stable usb supply
<wpwrak>
most hosts are fairly forgiving, but 220 uF may be pushing it
<azonenberg>
Yeah
<azonenberg>
Debating whether to go with a 10uf ceramic or a 47uf tant
<azonenberg>
since its after the bead
<wpwrak>
and they you can get fun effects like device power dancing around, with all the interesting things this may do to the FPGA's configuration process
<wpwrak>
again voice of experience here - in openmoko, we once had a board with an FTDI that also had tons of caps. we spent a good amount of time figuring out why the FTDI would seem to lose its flash (or eeprom, don't remember) content every once in a while ...
<azonenberg>
lol wow
<azonenberg>
yeah, i have a massive amount of capacitance on my SBC board
<azonenberg>
But it's also a LX16/25 plus DDR memory so it needs it
<azonenberg>
and its running on a wallwart
<azonenberg>
Good suggestions, guys... i should get this done more often
<azonenberg>
Going to fix up a bunch of stuff and add some debug points (scope ground clip etc)
<azonenberg>
then commit an updated version in a few hours... if nobody sees any problems in that version i'll send it out for first-round fab
<lekernel>
azonenberg: if you like a challenge, I'll have the M3 board to get done ;)
<azonenberg>
i don't think i'm quite that good at layout yet lol
<azonenberg>
i wouldnt mind looking over it and offering suggestions
<azonenberg>
which fpga are you using on it?
<lekernel>
artix-7
<lekernel>
azonenberg: btw I'm looking for potassium tantalate niobate (aka KTaNbO3 or KTN) crystals - any clues?
<azonenberg>
lekernel: ooh, artix
<azonenberg>
do you have a source for them yet or is this planning for the future?
<mumptai>
mhmm, for a laser scanner?
<lekernel>
planning
<lekernel>
yes, for a laser scanner
<azonenberg>
Also have you considered Zynq and, if you decided against it, what was your reasoning?
<lekernel>
I'm too cool for ARM
<azonenberg>
seems like the a9 would outperform LM32 by a huge margin
<mumptai>
and is it still covered by the webpack style tools?
<azonenberg>
mumptai: yes
<azonenberg>
So it's no less free than a proprietary FPGA with open RTL
<azonenberg>
a proprietary CPU with open code
<lekernel>
the RTL of that ARM is still closed
<azonenberg>
Correct
<azonenberg>
but so is the rtl for the boot loader on an FPGA that reads from SPI etc
<lekernel>
also, I don't like the messy interfaces that usually come with proprietary IP
<azonenberg>
I do agree with that
<azonenberg>
I wasn't recommending it, just curious as to your reasoning
<lekernel>
proprietary RTL, highly dependent on one vendor, shitty interfaces
<lekernel>
that rules it out for me
<azonenberg>
I see
<azonenberg>
re the crystals, no clue
<azonenberg>
i have a source for TaxClx
<azonenberg>
in ethanol solution
<azonenberg>
which upon spin coating and heating forms Ta2O5 for optical coatings, high-K, hardmasking, etc
<azonenberg>
thats the only tantalum compound i know where to get
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<azonenberg>
wpwrak: ok, so now the bottom right area by the jtag header has a 2x4 header of GPIO
<azonenberg>
cap is 47uF
<azonenberg>
i'll be adding a scope ground clip and some probe pads shortly
<wpwrak>
you stil need to fix the absolute paths in *.pro
<azonenberg>
added a 2x4 header for GPIO (eight signals, no power/ground) plus a ground clip for a scope and a bunch of labeled probe pads on the power rails and clock
<azonenberg>
still room for more probe pads in the upper right and between the fpga and jtag area
<azonenberg>
i just want to avoid breaking the ground plane under the GPIO traces at right center since those are LVDS capable and i want the option of decently high speed
<wpwrak>
you really ought to include power on the header
<azonenberg>
Six signals / 3V3 / gnd?
<azonenberg>
i cant fit more than 8 pins there
<wpwrak>
put it in the upper right corner ?
<wpwrak>
the bottom is way too crowded anyway
<azonenberg>
I'm puttnig stuff there too
<azonenberg>
i just dont want pins to go to waste
<wpwrak>
and the resistor facing the FPGA is nasty
<azonenberg>
which one?
<azonenberg>
the one above the led bank? thats actually a cap
<mumptai>
are the LDOs sufficient?
<azonenberg>
i run the same LDOs on my LX16 board
<azonenberg>
i wouldnt go any bigger but they're fine for a LX9
<azonenberg>
Header at bottom right is now 6 GPIO + 3V3 + gnd
<azonenberg>
mumptai: oh, and the LX16 board has DDR memory on it
<azonenberg>
without the RAM active it only pulls about 200 mA (800ish with the RAM going)
<azonenberg>
at max power they get up to 75C or so, a bit warm but well below the 125 upper limit
<wpwrak>
ah yes, the cap. a bit messy to solder that way
<azonenberg>
I'll move it to the underside
<azonenberg>
there are vias right there anywy
<mumptai>
k ;)
<wpwrak>
that solves the problem :)
<wpwrak>
what will go in the upper right corner ?
<wpwrak>
and you still need to fix the absolute paths ;-)
<azonenberg>
lekernel: lol the furnace i was going to get was a 4 inch cube, only $1200
<wpwrak>
"derating the simulator" nice. when you buy from xilinx, you can remember that some of your money goes to engineers that work specifically on making the products you're forced to use suck.
<azonenberg>
wpwrak: yeah lol
<azonenberg>
But its not like altera or lattice or actel is any better
<azonenberg>
and boycotting programmable logic entirely isnt a viable option
<wpwrak>
so the others also put code into their "free" tools that cripples them ?
<azonenberg>
I believe so
<azonenberg>
I dont know specifically about simulation model line counts
<azonenberg>
i know the free ones have device capacity limitations
<azonenberg>
and people wonder why folks like wolfspraul are making their own tools? :P