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<
GitHub144>
[migen/master] examples/fir: print Verilog source - Sebastien Bourdeauducq
<
GitHub144>
[migen/master] corelogic/record: better repr - Sebastien Bourdeauducq
<
GitHub144>
[migen/master] sim: multiread/multiwrite - Sebastien Bourdeauducq
<
GitHub11>
[migen/master] actorlib/sim: use set instead of list to represent active transactions - Sebastien Bourdeauducq
<
GitHub11>
[migen/master] actorlib: generator-based generic simulation actor - Sebastien Bourdeauducq
<
GitHub182>
[migen/master] Use super() instead of calling parent constructors directly - Sebastien Bourdeauducq
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<
GitHub112>
[migen/master] actorlib: WB reader simulation OK - Sebastien Bourdeauducq
<
GitHub112>
[migen/master] actorlib: WB writer simulation OK - Sebastien Bourdeauducq
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<
GitHub100>
[migen/master] flow/ala: fix typo - Sebastien Bourdeauducq
<
GitHub100>
[migen/master] flow/network: refactor graph - Sebastien Bourdeauducq
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