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<wolfspraul>
does anyone know why the ulogic debit project has vanished? what happened to Note and Rennaud?
<lekernel>
lack of interest
<lekernel>
they're doing fine
<lekernel>
they're not the only ones doing this btw, it seems recobus has gone further (but did not publish any source code)
<roh>
wolfspraul: what was it about?
<lekernel>
that one subject which is too hard for hackers
<lekernel>
bitstream analysis
<roh>
lekernel: its not too hard. its simply boring (from my pov)
<lekernel>
makes everyone go back to their little arduinos and 31337 stack overflows
<wolfspraul>
lack of interest prompts them to shutdown their site?
<wolfspraul>
well, a condescending attitude is rightfully rejected :-)
<wolfspraul>
that seems to be an aspect of free software culture I didn't know about before
<wolfspraul>
reminds me of my 3yr old
<lekernel>
sorry, years of accumulated frustration
<roh>
and usually hacking is unpaid, hard work with few people to support one even motivationally. so why do something where you know in advance that its a vendor-proprietary think you work on which they can change with the next release?
<wolfspraul>
hmm, ok
<wolfspraul>
you could make that point all over the place
<lekernel>
and yeah, free software culture has a lot of such aspects
<wolfspraul>
anyway I got it
<wolfspraul>
so it's gone, so what :-)
<roh>
lekernel: i can see your pain. but you also have to see that most people do not have the financial as also mental power to stay at some topic over years to come
<wolfspraul>
disagree, I think far more people than 'hackers' do this all the time
<wolfspraul>
if you mom has alzheimer, you may care for her for a looong time
<wolfspraul>
>95% of the world population has no means to hire a bunch of aids/helpers
<roh>
wolfspraul: sure. lots of hackers are 'doing it long term'
<wolfspraul>
was just trying to understand what happened to those 2 guys
<wolfspraul>
love strike :-)
<roh>
wolfspraul: usually opensource is less vendor-locked-in than the bitstream *hole
<lekernel>
like, everyone writing drivers for proprietary devices running on proprietary CPUs with a sometimes patented instruction set
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<roh>
lekernel: as long as you dont get asics done it doesnt matter
<roh>
your fpga world is atleast the same level of lock-in like when using free drivers on a commercial soc.
<wolfspraul>
roh I think that's too draconian
<wolfspraul>
look at the knowledge first, not the products
<roh>
wolfspraul: sorry, but exactly that is the truth.
<roh>
wolfspraul: and if that doesnt change, it will not be any more 'open' than we are atm.
<wolfspraul>
with that kind of attitude you will never conquer the knowledge for any digital design, running as fpga or hard wires
<wolfspraul>
people will care what the end result product can do
<roh>
wolfspraul: thats not true. stuff happens. people develop things. they just do not build soc.
<roh>
but using fpgas doesnt do that either. atleast not if you cannot time-warp it 5-10 years to history
<wolfspraul>
I started to learn about fpgas 2 years ago with milkymist, and every month I feel better :-)
<wolfspraul>
has a really great product come out of this yet? no
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<roh>
wolfspraul: ive also learned a lot. but mostly knowing that building any hardware with a soft-cpu will be a commercial fail
<roh>
seen that in the open and the commercial world now.
<lekernel>
roh: you know that you can run ASIC synthesis on something like 95% of the milkymist sources, right?
<roh>
lekernel: i know. can you use free tools for that?
<lekernel>
if you write them
<lekernel>
but knowing nothing about verilog or logic design will definitely not help you write such tools
<wolfspraul>
actually the xilinx fpgas come with a *mountain* of documentation
<roh>
lekernel: for a vendor proprietary platform without even proper documentation?
<wolfspraul>
is everybody clear about that?
<wolfspraul>
I cannot see how that is a bigger 'blob' than an Intel CPU or graphics card
<wolfspraul>
it's not
<lekernel>
roh: ASIC is just silicon. you are free to develop your own standard cell library, though I even remember stumbling across free ones.
<wolfspraul>
nobody is using free tools, but simply out of convenience
<roh>
wolfspraul: actually we do not have any binary drivers left on normal pc hardware.
<wolfspraul>
yeah. you hardwired it :-)
<roh>
wolfspraul: only firmware which gets executed on different cpu/frontends
<wolfspraul>
fpgas are fun. great documentation, and great changes for innovation with free tools. I see the upside.
<roh>
lekernel: my point is: as long as we do not have a way to produce such an asic, i do not have any interrest to sink money or time in such a thing.
<wolfspraul>
chances
<wolfspraul>
then don't
<wolfspraul>
btw the thing I am talking about nowadays I call 'digital design', not 'fpga' vs 'asic'
<roh>
i know that its a part of what needs to be done. but its an really expensive one which also is a showstopper
<lekernel>
long live arduino and rpi, heh? at least that's cheap :)
<roh>
lekernel: thats not my point.
<roh>
lekernel: there are thousand of soc out there. no shortage.
<roh>
lekernel: but you have to understand that nobody will pay more money for less performance
<lekernel>
I doubt the mirteo will have less performance for anything user-visible.
<lekernel>
and also we're talking about logic design here, not FPGA/ASIC
<lekernel>
as wolfspraul said
<lekernel>
that's the same no matter what physical technology you are targeting
<roh>
lekernel: no questions on custom logic designs. you will get those fast enough.
<wolfspraul>
don't understand
<roh>
but if one wants to run something with an ipstack, anything below real 200mhz is childish at best
<wolfspraul>
who will get what?
<wolfspraul>
I read about an IC startup the other day, their speciality are audio cores
<lekernel>
roh: and you know LM32 (the very same verilog sources) runs at 800 in 90nm ASIC, right?
<wolfspraul>
and all their marketing is about how *low* megahertz their cores can go
<wolfspraul>
for example full mp3 decoding in 6 mhz
<wolfspraul>
etc.
<wolfspraul>
just saying
<wolfspraul>
there are different perspectives into this
<roh>
means: i thought about it a lot, and i dont see any proper way to get something like lm32 fast enough on an fpga
<lekernel>
roh: therefore you don't learn logic design?
<roh>
lekernel: you dont get it, do you? i know electronics.
<roh>
but i HATE the xilinx tools
<roh>
any i havent learned about somebody who works with fpgas who doesnt.
<roh>
as long as that doesnt change, people like me and thousands more will continoue to avoid that. even when needing to use different hardware then.
<lekernel>
judging from the number of verilog/vhdl patches you have submitted, be it in this project or in another, I doubt you really know everything about electronics :)
<roh>
i really like the idea to get stuff working on low mhz. means a lot of optimization. the sad thing is: you get a 400mhz cpu for 3$. but a developer to make code even twice as fast costs atleast 20times that.. PER HOUR.
<lekernel>
so, take that to your advantage
<roh>
lekernel: i think you need to be carefull what you say about people. i do electronics for over 10 years now. and i know why i dont do fpgas. nobody wants to buy them if avoidable.
<lekernel>
then do asics :)
<lekernel>
it's the same on the vhdl/verilog layer
<roh>
ive seen people add multiple really fast arm cpus to stuff.. why? because they could write the code in-house and the hw is cheap. and devels only needed a few days in total. for even one fpga they would have needed multiple times the project budget.
<roh>
lekernel: if you learn about a way to do small amounts of asics for serious prices, holler. if it still needs a multi-million dollars, people will continue to use cheap fast clocked arm and mips cores
<roh>
there is a reason juniper doesnt build in asics. A) its cheaper to use fpgas (not enough volume for an asic) and b) designs are changed too often/fast c) money on hardware doesnt matter on such products
<roh>
as long as you dont have such a high-price, high-performance product and the customers with enough need for them, its really hard keeping a fpga based business afloat.
<lekernel>
you've been saying that for years...
<lekernel>
and I still disagree. no need to repeat those arguments again.
<roh>
lekernel: i havent seen any arguments from your side so far.
<roh>
lekernel: i really do not want to talk down your projects of motivation. on the contrary. but i also really would like to see something where a realistic chance on making it happen as product in a pricerange, which the targeted customers can afford is possible.
<roh>
atm i fear i will never get a mm1 sold. the last guy was interrested but doesnt have that money. all these artists are even more broke than me
<lekernel>
ever heard of thecrucible.org ?
<roh>
the other ones all use matrox multihead stuff and need multiple vga ports and do lots of mapping
<lekernel>
look at their prices :) and they're all artists. and they do great shit I've been looking for FOR YEARS in Europe.
<roh>
lekernel: i know what people who do the hard work on parties are paid. thats crap. one cannot survive of that.
<roh>
most get some money from the social services or have extra other jobs. atleast the vjs i met so far.
<lekernel>
so. FPGA on M1 is $40. ARM SoC is $5. what would a $35 rebate do?
<roh>
i think the mm would be a good device for clubs and similar fixed installs. just make it go 'auto-vj'
<lekernel>
I agree there might be problems on the M1, but don't blame the FPGA
<lekernel>
s/might be/are
<roh>
lekernel: the vendors save CENTS. they use cheaper, more crappy resistors and caps to get some more cents out of production. its bad. i agree that it would be nice. but as long as it doesn work financially its hard.
<lekernel>
we're not in this sort of volume
<lekernel>
for the M1, the bottom line of FPGA vs. proprietary SoC is a $35 saving
<lekernel>
period :)
<roh>
lekernel: and the lower performance compared to an asic.
<lekernel>
no.
<roh>
atleast when it comes to clocks.
<roh>
can you make something atleast work in the 400mhz cpu clock region?
<lekernel>
I don't need to
<roh>
only if you reinvent the wheel completely.
<lekernel>
oh, no
<roh>
and yes you need to. people do not even buy smartphones which cannot do 720p h264 decode anymore.
<lekernel>
things like migen flow aren't in the industry at all
<lekernel>
even in the billion-dollar proprietary ASIC one
<roh>
power of 'getting work done' is everything. if you cannot make it by clock, you need to go parallel. even amd and intel suck on that big time
<lekernel>
because of legacy
<wpwrak>
why do i feel as if i was overhearing the neighbourhood dogs fighting ? :)
<roh>
lekernel: not only that. often problems are simply not possible to solve in parallel
<lekernel>
they probably spend most of their resources on legacy and supporting pesky features without bugs like USB or chinese DDR3 SODIMMs
<roh>
lekernel: well.. make the mm1 handle multiple hd screens in parallel and you got a winner.
<roh>
continue on one xga one, i still cant sell it.
<lekernel>
great
<lekernel>
I'm doing that right now
<roh>
and make sure you have vga support.
<roh>
and usb (no way around)
<wpwrak>
roh: multiple HD screens in parallel should be no problem at all. already m1rc3 should be able to handle about 4 of them, as long as you don't mind analog.
<roh>
wpwrak: ive not seen resolutions above xga on it at all (and ar enot sure the dac can do them)
<roh>
wpwrak: people use the matrox triplehead a lot here. it concatenates up to 3 vga screens (also avail in dvi) next to each other into one 'wide screen' which the computer then drives
<wpwrak>
dunno about the DAC chip. but a nice little external resistor network will go as fast as you care to drive it. high resolution is no problem at all.
<wpwrak>
in fact, an FPGA is perfect for that :)
<roh>
wpwrak: the dac has a given bandwith. that limits the whole thing on the end.
<wpwrak>
sure. ah, you'll of course need a bit of extra hardware for the additional connections.
<wpwrak>
then program the desired number of HD signal generators and voila, a great number of screens running at an amazing resolution :)
<roh>
wpwrak: you forget the memory bandwith. ;)
<wpwrak>
did i ? :)
<roh>
1x vga is something like ~70mbyte/second. and you need to do more than just read it out
<wpwrak>
did i promise a frame buffer, too ? you asked for resolution :)
<roh>
1x fullhd is 474mbyte/second (read only)
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<roh>
wpwrak: no framebuffer, no reason to drive the ramdac at all ;)
<roh>
if you dont find a possibility to render every pixel in realtime on readoout ;)
<wpwrak>
oh, you can still arithmetically generate some pattern. maybe it even looks somewhat interesting. who knows :)
<wpwrak>
yup, that's the idea. think efficient :)
<roh>
wpwrak: i think you know that i am usually not in the mood for senseless could-be-may-bes ;)
<roh>
anyhow. thats about the 'rough' spec of needed memory bandwith. so yeah. the ddr3 is neccessary (bandwith wise) .. but it still needs some really high clocks for even pushing the data
<lekernel>
roh: ...and look at the -ng code. you'll see that it generates several DRAM commands in parallel, loads them into a shift register and pushes them out with a phase aligned multipled clock that can go up to 1GHz
<roh>
nice
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