lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<GitHub88> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/7d0e179a035e4f9d8517250d4737d5dce169647b
<GitHub88> [migen/master] actorlib: structuring (untested) - Sebastien Bourdeauducq
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<GitHub75> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6fac3f027fc9c5bd779ee47e566b8065f8659356
<GitHub75> [migen/master] examples/dataflow: structuring test - Sebastien Bourdeauducq
<GitHub76> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/9a38c47048b2f7de0883d95342704587a228098f
<GitHub76> [migen/master] examples/dataflow/structuring: test Cast - Sebastien Bourdeauducq
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<Fallenou> hum why initial statement does not work in ISim ? =(
<lekernel> it should...have you tried on a simple example?
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<Fallenou> sys_rst value is 1'bx during one clock period at startup
<Fallenou> even with initial begin sys_rst <= 1'b1; end in m1reset.v
<lekernel> that's not a simple example, that's thousands of lines of verilog code
<Fallenou> I replaced initial begin sys_rst <= 1'b1; end by "reg sys_rst = 1'b1;" and it works now
<lekernel> is the rest of your testbench code in another initial block?
<lekernel> it could be that it waits for your testbench to complete to execute sys_rst <= 1'b1
<Fallenou> it's not really a testbench it's a migen generated soc.v
<Fallenou> but not up to date migen, old migen
<lekernel> er, it won't simulate alone anyway
<Fallenou> is it OK if I use this kind of initialization reg XX = value; ?
<Fallenou> just for the reset
<Fallenou> other regs (in lm32 cpu) are initialized upon reset
<lekernel> should be ok... but the initial statement should also work
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<Fallenou> yes I think too
<Fallenou> ok so my problem is not reset related ^^
<Fallenou> I'm accessing the data cache blockram with index 000, , next clock the data_out is "XXXX"
<Fallenou> why the hell address 000 of the blockram is not initialized ...
<Fallenou> strange thing is I just flushed I and D caches
<Fallenou> so it should clearly have a value
<lekernel> i'd rather elucidate this initial statement problem
<Fallenou> ok :)
<lekernel> especially if you notice strange X's before
<lekernel> verilog bugs like to hide under such discrepancies
<Fallenou> well now I don't have any X any more at system startup which is great
<Fallenou> at least I know the state of all my modules should be correct
<Fallenou> all FSM should start with the correct state
<Fallenou> hum maybe it's important to have afew nops right after each cache invalidation
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<Fallenou> hum ok it never enters the flush state
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<Fallenou> ok tags get written to during a flush, but data does not get written to , which explains the cache flush does not prevent me from XXX
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<Fallenou> too bad there is no pattern search in ISim
<Fallenou> to search for a specific combination of wire/reg value
<Fallenou> or a trigger or something
<Fallenou> it's quite painful to scroll in all this mess
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<wpwrak> and the joy of closed source is that you can't just add such a thing
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<Fallenou> hehe true
<kristianpaul> so not get used to it! :)
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<GitHub163> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/34d8ae3c11eeb366320544a3ecdfc1479a9c93f9
<GitHub163> [migen/master] flow: perftools - Sebastien Bourdeauducq
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<mwalle> Fallenou: is there any documentation about your mmu design yet?
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<GitHub110> [migen] sbourdeauducq pushed 4 new commits to master: https://github.com/milkymist/migen/compare/34d8ae3c11ee...956d1257c2bf
<GitHub110> [migen/master] actorlib/structuring/Pack: drive busy signal - Sebastien Bourdeauducq
<GitHub110> [migen/master] actorlib/sim/SimActor: remove dead time between transactions - Sebastien Bourdeauducq
<GitHub110> [migen/master] flow/perftool: fix cpt equation - Sebastien Bourdeauducq
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