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<lekernel>
wpwrak: yeah, yeah, continue being sarcastic. meanwhile, linux/x11 don't work while rtems/mtk do (also using cooperative multitasking for the UI by the way)
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<lekernel>
done in a more messy way than with lua coroutines even
<lekernel>
I agree that it won't work in the general case, it's enough here.
<lekernel>
s/it's/but it's
<lekernel>
also 100% of the linux UIs are shitty, so it has to be NIH. so why the bickering? :)
<Fallenou>
NIH = ?
<Fallenou>
not invented here ?
<lekernel>
mwalle: not much difference, simply using the migen CSR bank generator
<GitHub131>
[milkymist/master] softusb: interrrupt support for navre - Michael Walle
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<Fallenou>
it seems the cache is behaving correctly right now, it's part of the test "detest"
<Fallenou>
I map a->a, I write 42 to a, I read back from a, I write 43 to b, I map a->b, I read back from a, and it reads 43 , not 42
<Fallenou>
and without any cache flush
<lekernel>
when writing, you are reading the TLB, then sending the write directly and immediately on the bus, right?
<Fallenou>
yes I did not change the way the cache works
<Fallenou>
it's still write through
<Fallenou>
it's written both on the bus and in the cache at the same time
<Fallenou>
tlb does its lookup when the instruction is still in the X stage
<Fallenou>
so that when the instruction reaches the M stage, the tlb lookup is already done and ready
<Fallenou>
just like the cache in fact
<lekernel>
how do you inhibit the write into the cache on a TLB miss?
<lekernel>
(you'll see... itlb will be easier ;) read only, no permission bits, ...)
<Fallenou>
13:50 < lekernel> how do you inhibit the write into the cache on a TLB miss? < I can't see where it's done in the code so I guess it's not done and it's a bug :) I will test that ! thanks for pointing that out
<Fallenou>
I would just do something like assign write_port_enable = ((refill_ready == `TRUE) || !stall_m) && ~dtlb_miss;
<lekernel>
the problem is the write is already done when the TLB data becomes available
<lekernel>
maybe the solution would be to revert the write on a TLB miss
<lekernel>
or invalidate the whole cache line
<wpwrak>
lekernel: (dirty) it's for swapping, rw-mapping files, and so on. the memory manager needs to know when a page has changed so that it only has to write things that have actually changed.
<lekernel>
if you want to implement #1, it is possible to configure block-RAMs so that they output the previous data on a write
<lekernel>
you just have to describe it in the verilog, and the synthesizer will (usually) do the right thing
<wpwrak>
lekernel: you can assume all pages are dirty, but i'd expect this to be pretty inefficient
<Fallenou>
yes I've seen that in Xst doc
<lekernel>
just do whatever is easier... since you have to run slow software on a TLB miss, the performance gain of #1 over #2 is negligible
<wpwrak>
lekernel: (nih) i'm a bit surprised you suddenly see a need to go in a new direction with the underlying OS. linux infrastructure is coming along nicely, so why spend now weeks on reinventing the ROM BASIC ?
<lekernel>
maybe you could even modify the cache control system to let the software invalidate individual lines
<Fallenou>
I think it should be pretty easy to allow invalidating cache lines
<Fallenou>
it's already possible to invalidate just one TLB line
<lekernel>
would save you the pain of implementing the little stall cpu/multiplex cache control/invalidate line sequencer in hardware
<wpwrak>
(NIH) and RTEMS seems give little enough trouble at the moment that there doesn't seem to be a pressing need to abandon it in a hurry
<lekernel>
wpwrak: one of the points is also to evaluate LLVM, and building RTEMS with clang is messy
<lekernel>
not because of LLVM but because of autocrap
<Fallenou>
I guess a CC=clang isn't enough ? :)
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<lekernel>
with my last clang patch, in theory it should be enough... except you also need -ccc-host-triple lm32-elf in the cflags
<wpwrak>
i have my hopes set on autocrap behaving a little better on linux. at least the OS environment will be known. but yes, autocrap will be more visible on linux.
<lekernel>
and autocrap is all about prefixing tool names (e.g. lm32-elf-xxxx), not passing the arch in the cflags
<lekernel>
so much for something meant to make software portable ...
<lekernel>
wpwrak: calling it a "rom basic" is a bit like calling a ferrari a renault 4L
<lekernel>
besides, I'm not reinventing much - it's a lot of libs and copy and paste - except stuff like the graphics/rendering toolkit which is non-existent in linux anyway
<stekern>
lekernel: do you need the -ccc-host-triple if you make a symlink called lm32-elf-clang?
<lekernel>
maybe not... but I like the -ccc-host-triple. having one compiler per architecture while >80% of the code is shared is stupid.
<lekernel>
wpwrak: is the javascript in your browser a rom basic as well? :)
<stekern>
well, it still the same compiler with all the targets compiled in. i.e. lm32-elf-clang == clang -ccc-host-triple lm32
<stekern>
you can still run clang -ccc-host-triple mips if you like
<lekernel>
sure. but why keep the gcc legacy, except for supporting inane tools like autocrap?
<lekernel>
besides I'm pretty sure there will be other problems
<stekern>
oh, yes, probably
<lekernel>
Fallenou: I kinda like the software cache line invalidation. otherwise you need to mux cache access, stall the CPU, etc.
<lekernel>
more LUTs, more delay (ie less MHz), more complexity, more probablity of nasty bugs
<lekernel>
if you implement the per-line invalidation, maybe you can even remove the current mechanism that invalidates the whole cache (it's just a counter + sequencer)
<lekernel>
you could do that counter in software. not sure how slow it will be compared to the hardware counter, though.
<wpwrak>
(rom basic) i mean as a simple language that's "hardwired" into the platform
<lekernel>
take it as an additional means of doing modifications
<wpwrak>
and the silly javascript in my brower is that i rarely have to worry about it, let alone write a libc for it ;-)
<lekernel>
the rest of the software is still open source, and you are free to modify it - if you feel like installing a toolchain, recompiling, etc.
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<lekernel>
also, lua allows you not to worry about things like memory management, annoying C string manipulations, etc.
<Fallenou>
if it's working correctly I think it's best to keep the hardware implementation for invalidating the whole cache
<Fallenou>
it's really more efficient
<wpwrak>
i'm not against lua. one can probably learn it in a day.
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<Fallenou>
but yes OK I will add a way to invalidate just one cache line, I will need to be smart to multiplex CSR though :) it's a scarce resource
<wpwrak>
i just find it odd that you write your own operating system around it
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<Fallenou>
I'm already doing different things whether you rcsr or wcsr with the same CSR ID
<Fallenou>
rcsr dtlbvaddr gives you the virtual address of latest page fault, wcsr dtlbvaddr writes to the dtlb_vaddress_reg register which is used to set up a mapping
<Fallenou>
or to invalidate a line
<Fallenou>
in the rcsr dtlbvaddr case I defined an alias "dtlbma" (dtlb miss address) to "dtlbvaddr" in binutils in order to keep source code readability
<lekernel>
Fallenou: when you write to DCC, you give a register no?
<lekernel>
iirc the value is ignored atm
<Fallenou>
afaik yes the value is ignored
<lekernel>
you can say that if bit 31 is set, then it only invalidates one line determined by the other bits in that reg
<Fallenou>
a simple write is enough to trigger invalidation
<Fallenou>
hum that breaks software compatibility but ok
<lekernel>
who cares
<Fallenou>
ok =)
<Fallenou>
I'm already using that kind of trick for DTLBCTRL csr
<lekernel>
and iirc software uses r0 atm, so it wouldn't even break
<Fallenou>
if bit 31 is set it's targetting DTLB, if not it's targetting ITLB
<lekernel>
maybe "DTLBCTRL" is a ill-chosen name then :)
<Fallenou>
it's TLBCTRL actually
<lekernel>
good
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<Fallenou>
to help spot problems with the MMU, in parallel of writting "hard written" test sequences, I will implement a few commands to directly play with the MMU from the bios prompt
<Fallenou>
like "map", "invalidate"
<Fallenou>
memory read and memory write are already implemented afaik
<Fallenou>
so that one can directly try a scenario by just entering a few commands
<Fallenou>
to check if it's supported or behaving correctly :)
<Fallenou>
like write there, map this, read back there, invalidate this etc etc
<Fallenou>
it won't spot tricky timing problems, but will spot big implementation problems :)
<Fallenou>
cache coherency and such
<wpwrak>
sounds reasonable
<Fallenou>
and quick to implement :
<Fallenou>
:)
<Fallenou>
helpful and quick
<wpwrak>
you may want to do cached and uncached reads and maybe even writes, so that you can also set up or test unusual situations
<Fallenou>
wpwrak: I think I may not have understood all your emails about page dirty and such, I may ask you some questions about it later ^^
<wpwrak>
sure :)
<Fallenou>
thx
<wpwrak>
my memory on those things is a bit dated. i looked into paging quite a bit when i implemented "zero-copy" for ATM, but that was about 16 years ago
<Fallenou>
aouch
<Fallenou>
I was still drinking milk
<wpwrak>
linux was still in its infancy back then as well ;-)
<lekernel>
I remember running your LILO on my 486 :)
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<Fallenou>
wpwrak: you are the original author of LILO ?
<wpwrak>
Fallenou: yup :)
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<Fallenou>
ohoh I used it too :p but not on my 486 ^^
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<GitHub186>
[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/y_bdnA