<GitHub170>
[migen/master] wishbone: base TargetModel class - Sebastien Bourdeauducq
* Fallenou
started ITLB part, fearing first test
<Fallenou>
it's gonna blow !
* lekernel
is preparing an army of simulation modules to help when the dataflow + asmi blows up
<Fallenou>
hehe
<Fallenou>
ok let's try ITLB
<Fallenou>
fire in the whole !
<Fallenou>
hum ok it does not blow, but does it really work ?
<Fallenou>
let's try a more difficult mapping than map(f, f); f();
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<wpwrak>
it's better if it doesn't work on the first try. otherwise, you'll be endlessly suspicious about it
<Fallenou>
with map(f, some_address); some_address(); it blows :)
<Fallenou>
I am trying inserting a few nops() between ITLB activation and the actual "call" to the function
<Fallenou>
it does not work any better, I should go back to simulation
<Fallenou>
ok enough playing around blindly with the FPGA, let's go back to ISim =(
<roh>
wpwrak: *g*
<roh>
wpwrak: i know that feeling... 'does it work? seems so... but do i trust it to stay that way?'
<wpwrak>
Fallenou: there's no glory in too easy a victory :)
<Fallenou>
indeed, let say that :p
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<Fallenou>
I'm scratching my head to find out how to do enable ITLB in a clean way
<Fallenou>
I have some code at physical page X, I map virtual page Y to physical page X
<Fallenou>
if I do something like wcsr tlbctrl, ENABLE_ITLB then call Y
<Fallenou>
and let say instructions after the "call Y" are : inst_A inst_B
<Fallenou>
it will page fault when fetching inst_B
<Fallenou>
cause there is no mapping for the page which is executing (in the kernel space)
<Fallenou>
the cpu will fetch inst_A and inst_B anyway, even if there is a "call Y" instruction
<Fallenou>
they won't be executed though (inst_A and inst_B)
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<Fallenou>
how can I prevent this kind of page fault which should not occure
<Fallenou>
I could add a mapping for the code currently running (the kernel code which enables the ITLB) but it's not clean and it could/will generate bugs, for instance if the user space application is using the exact same virtual address for something
<Fallenou>
I could delay the effect of the wcsr ... and acutally enable ITLB only 2 instruction later
<Fallenou>
let's try that :o
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<Fallenou>
hum hum it fetches the correct translated addresses now :)
<Fallenou>
but after fetching a few instructions it generates a page fault
<Fallenou>
without changing of page :o weird
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<Fallenou>
it seems ld is not happy with me using "bi" instruction
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<Fallenou>
it works :)
<Fallenou>
at least I have one working example :p
<Fallenou>
but it's a start !
<Fallenou>
let's commit this
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<GitHub179>
[milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/GL1hOg
<GitHub179>
[milkymist-mmu-simulation/master] Add a draft of ITLB to Milkymist MMU - Yann Sionneau
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<GitHub115>
[milkymist-mmu] fallen pushed 2 new commits to mmu-bios: http://git.io/koOaoQ
<GitHub115>
[milkymist-mmu/mmu-bios] Add support for ITLB in simulation BIOS - Yann Sionneau
<GitHub115>
[milkymist-mmu/mmu-bios] Add a simple test for ITLB in simulation BIOS - Yann Sionneau
<Fallenou>
gn8!
<Fallenou>
hi xiangfu !
<xiangfu>
Fallenou, Hi
<Fallenou>
how are you ?
<xiangfu>
fine. :)
<xiangfu>
recently don't have time working on m1.
<Fallenou>
congratz for your latest openwrt sync with upstream on the ben :)
<Fallenou>
yeah I saw that
<Fallenou>
but you seemed to have been busy ;)
<xiangfu>
yes.
<xiangfu>
Fallenou, what about add 'milkymist-mmu' to build host?