<mwalle>
still needs some more tests (eg ITLB isn't covered at all), tlb miss handler exception is wrong, USR bit not implemented yet
<mwalle>
Fallenou: wpwrak: lekernel: so what do you think, one or two exception handlers?
<Fallenou>
I guess it's cleaner to only have one exception handler for all MMU related stuff (*tlb miss, protection fault (read/write/execute)) ?
<Fallenou>
dunno honestly
<Fallenou>
I did two separate because in my head dtlb and itlb are really two different things
<Fallenou>
but both could be handled in the same exception handler actually
<wpwrak>
mwalle: i guess we should try either and benchmark.
<Fallenou>
a lot of benchmarks :)
<Fallenou>
well I don't know if there would be differences
<Fallenou>
that's just an extra "if" in the handler
<wpwrak>
you could of course have a "set TLB that caused the last exception" operation :)
<wpwrak>
and i'd separate TLB miss from permission or page fault. TLB miss can be a very streamlined piece of code and should run very often in comparison to the others.
<Fallenou>
that would not be hard to implement a bit in PSW that would be 0 if last TLB miss was DTLB, and 1 for ITLB
<Fallenou>
something like that
<Fallenou>
wpwrak: ok why not
<mwalle>
Fallenou: use an own register for the cause, not the psw, because thats the processor state
<Fallenou>
mmu state ?
<Fallenou>
create another extra CSR ?
<mwalle>
Fallenou: or use TLBCTRL for reading
<Fallenou>
oh, right
<mwalle>
Fallenou: in mips its named BADADDR and CAUSE register
<mwalle>
wpwrak: maybe we should actually write a performant tlb miss handler and see what the hw can do to optimize it
<mwalle>
but not now, i'm going to bed ;)
<Fallenou>
the same here
<Fallenou>
I can't think straight anymore
<Fallenou>
worked on itlb at least 15 hours this week-end :)
<Fallenou>
gn8!
<mwalle>
gn8
<Fallenou>
oh, and thanks for the qemu commits !
<mwalle>
np, i guess the interesting part is the test_mmu.S
<mwalle>
inn tests/tcg/lm32/
<Fallenou>
:)
<Fallenou>
sure
<wpwrak>
mwalle: yeah, a reference TLB miss handler would be a good thing to have. not sure how close to the real thing you can get without actually writing the real thing, though.
<wpwrak>
(or making the difference trivial)
<Fallenou>
maybe you can just think of what you'd like the hardware to provide (informations in registers etc)
<Fallenou>
for the software to be as straight forward to write
<Fallenou>
and as fast and efficient as possible
<Fallenou>
while writting the C-like code, I think the idea of what you need and how you would need it to be efficient would come to mind
<wpwrak>
so .. 1) the register that holds the VA that caused the miss should be the same as the one that holds the VA for updating the TLB. 2) the code could be even shorter if a write to the PA register implicitly triggers a TLB update