lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<GitHub37> [linux-milkymist] larsclausen pushed 1000 new commits to master: http://git.io/R-DlUg
<GitHub37> [linux-milkymist/master] Btrfs: fix locking in btrfs_destroy_delayed_refs - Josef Bacik
<GitHub37> [linux-milkymist/master] Btrfs: wake up transaction waiters when aborting a transaction - Josef Bacik
<GitHub37> [linux-milkymist/master] Btrfs: abort the transaction if the commit fails - Josef Bacik
<Fallenou> wow 1000 commits, you are committing quite fast ;)
<larsc> took half an hour to even push those commits
<Fallenou> ahah
<Fallenou> you can't even visualize them using the github link provided on irc
<Fallenou> error 500 :)
<Fallenou> larsc: did you try to boot it up ?
<Fallenou> I tried a few days ago I got nothing in my uart console
<larsc> Fallenou: yes
<larsc> I get a shell
<Fallenou> oh, weird
<larsc> you need to pass 'console=ttyS0' to the kernel command line
<Fallenou> oh right :)
<Fallenou> I was not using any cmdline
<larsc> unfortunately something in libc's execvp is broken and I can't spawn any other process
<Fallenou> arg
<mwalle> Fallenou: i just need the VADDR for invalidating, right?
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<Fallenou> yes
<Fallenou> vaddr only is enough
<Fallenou> pfn(vaddr)
<Fallenou> you can set the page offset bits to whatever you want, they will get ignored
<Fallenou> does someone have another opinion on the 4 kB / 8 kB page size ?
<Fallenou> or even 16 kB :)
<larsc> hm the bug seems to be a compiler bug, or whatever, the mmap implementation in libc got doesn't set the signal numner :/
<larsc> mwalle: do you remember the problem we had with the register write to r8 being optimized out? Didn't we fix that?
<larsc> with this crazy hack in the kernel it works:
<larsc> + ori r3, r0, 135
<larsc> + bne r8, r3, 1f
<larsc> + ori r3, r0, 4095
<larsc> + bne r2, r3, 1f
<larsc> + mvi r8, 222
<larsc> +
<mwalle> larsc: na that was discussed on gcc ml
<mwalle> but was never fixed / seen as a problem
<larsc> but I think we had a workaround for it
<mwalle> larsc: yeah
<mwalle> but i dont remember
<mwalle> some syscalls didnt work
<larsc> i guess that's the one
<larsc> yea, that's it
<mwalle> that was the ML thread
<mwalle> Fallenou: i guess we can test it and make some measurements and then decide whats the best page size
<Fallenou> yeah I guess
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<larsc> yeay, with that fix it works fine again
<mwalle> Fallenou: how can i distingish between and itlb and dtlb miss in the exception?
<GitHub146> [milkymist-mmu] fallen pushed 1 new commit to mmu: http://git.io/3E7MZg
<GitHub146> [milkymist-mmu/mmu] Add ITLB and PSW CSR register and a little bit of refactoring - Yann Sionneau
<Fallenou> mwalle: 2 different exception vectors
<Fallenou> see in the commit I just pushed, in crt0.S
<mwalle> Fallenou: would it be possible to put them into one and make a cause register?
<mwalle> because once we have some more functionalities like protection bits, the have to be a cause register anyway
<Fallenou> the cause bits would need to be saved upon exception
<Fallenou> so it will end up in PSW I guess ?
<mwalle> Fallenou: mh? it would be the same handling as the BADADDR register
<mwalle> dunno how you named it TLBMA ?
<mwalle> set CAUSE + BADADDR, raise exception
<Fallenou> in theory another tlb miss should not happen while in tlb miss handler
<Fallenou> so I guess there is no point in saving CAUSE+BADADDR upon exception like ITLBE is saved in EITLBE
<Fallenou> right ?
<mwalle> Fallenou: once there is an miss exceptions both translations are disabled, so there can't be any more TLB miss exceptions
<Fallenou> right -_-
* Fallenou tired
<mwalle> Fallenou: if theres a miss while loading 0x1004, do i get the BADADDR 0x1004 or 0x1004 & PAGE_MASK == 0x1000 ?
<Fallenou> you get the whole address
<mwalle> Fallenou: fine :)
<Fallenou> itlb is better now but those last bugs are really annoying
<Fallenou> really a pain
<mwalle> hehe ;)
<Fallenou> crazy, I just add a new function in BIOS prompt (itlbi to flush whole ITLB)
<Fallenou> and now I run itlbtest , which has NOTHING to do with the new bios prompt function
<Fallenou> and now instead of behaving nicely, I got a storm of exceptions
<Fallenou> EA is set to the address of the exception handler and it goes in infinite loop of exception handling
<Fallenou> is my stack smashed or what ?
<Fallenou> am I going to hardcode in the verilog code "if (pc != 0x4400120) ea <= pc" ? :)
<Fallenou> I see, the joke is not funny :p
<mwalle> just pushed the qemu repo
<mwalle> still needs some more tests (eg ITLB isn't covered at all), tlb miss handler exception is wrong, USR bit not implemented yet
<mwalle> Fallenou: wpwrak: lekernel: so what do you think, one or two exception handlers?
<Fallenou> I guess it's cleaner to only have one exception handler for all MMU related stuff (*tlb miss, protection fault (read/write/execute)) ?
<Fallenou> dunno honestly
<Fallenou> I did two separate because in my head dtlb and itlb are really two different things
<Fallenou> but both could be handled in the same exception handler actually
<wpwrak> mwalle: i guess we should try either and benchmark.
<Fallenou> a lot of benchmarks :)
<Fallenou> well I don't know if there would be differences
<Fallenou> that's just an extra "if" in the handler
<wpwrak> you could of course have a "set TLB that caused the last exception" operation :)
<wpwrak> and i'd separate TLB miss from permission or page fault. TLB miss can be a very streamlined piece of code and should run very often in comparison to the others.
<Fallenou> that would not be hard to implement a bit in PSW that would be 0 if last TLB miss was DTLB, and 1 for ITLB
<Fallenou> something like that
<Fallenou> wpwrak: ok why not
<mwalle> Fallenou: use an own register for the cause, not the psw, because thats the processor state
<Fallenou> mmu state ?
<Fallenou> create another extra CSR ?
<mwalle> Fallenou: or use TLBCTRL for reading
<Fallenou> oh, right
<mwalle> Fallenou: in mips its named BADADDR and CAUSE register
<mwalle> wpwrak: maybe we should actually write a performant tlb miss handler and see what the hw can do to optimize it
<mwalle> but not now, i'm going to bed ;)
<Fallenou> the same here
<Fallenou> I can't think straight anymore
<Fallenou> worked on itlb at least 15 hours this week-end :)
<Fallenou> gn8!
<mwalle> gn8
<Fallenou> oh, and thanks for the qemu commits !
<mwalle> np, i guess the interesting part is the test_mmu.S
<mwalle> inn tests/tcg/lm32/
<Fallenou> :)
<Fallenou> sure
<wpwrak> mwalle: yeah, a reference TLB miss handler would be a good thing to have. not sure how close to the real thing you can get without actually writing the real thing, though.
<wpwrak> (or making the difference trivial)
<Fallenou> maybe you can just think of what you'd like the hardware to provide (informations in registers etc)
<Fallenou> for the software to be as straight forward to write
<Fallenou> and as fast and efficient as possible
<Fallenou> while writting the C-like code, I think the idea of what you need and how you would need it to be efficient would come to mind
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<wpwrak> hmm ... uint32_t **ptd = PAGE_TABLE_DIRECTORY_ADDR; addr = VA_REG; /* forgot the name */ uint32_t *pt = ptd[addr >> 22]; if (!pt) goto no_page_fault; uint32_t pte = pt[(addr >> 12) & 0x1023]; if (!pte) goto no_page_fault; PA_REG = pte; CMD_REG = CMD_WRITE_TLB; return;
<wpwrak> all if (x) would be if (unlikely(x)) (not sure this matters in this case, though)
<Fallenou> wo wo, please, post this in a pastebin, or a piratepad to allow other to modify :p
<Fallenou> it's unreadable on 1 line
<wpwrak> so .. 1) the register that holds the VA that caused the miss should be the same as the one that holds the VA for updating the TLB. 2) the code could be even shorter if a write to the PA register implicitly triggers a TLB update
<wpwrak> i'll post to the list
<Fallenou> ok great :)
<Fallenou> 1) it's the case
<Fallenou> 2) very good idea !
<Fallenou> http://piratepad.net/RSE6AWxIIa < the piratepad of when I started to think about the mmu
<Fallenou> a lot of what's written there is out of date
<Fallenou> but I just added a TODO at the bottom
<Fallenou> feel free to write things in it
<Fallenou> (and notify me when you do :p)
<Fallenou> going to bed, gn8!
<wpwrak> i'll just stick with mail. don't like to scatter discussions over a dozen different media ;-)
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