<lsneff>
Has anyone tried getting nmigen running in a python interpreter compiled to wasm?
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<lsneff>
I'm uploading code to a tinyfpga bx and I'm able to upload the code and it seems to work, but the uploading fails after success with an error code returned by tinyprog
<anuejn>
having that done makes me really happy :D
<_whitenotifier-f>
[nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTFgW
<_whitenotifier-f>
[nmigen/nmigen] whitequark 9cc82d8 - Deploying to gh-pages from @ b15f0562a62ebbd48b87f2d662cd01845c857c62 🚀
<whitequark>
anuejn: me too, since it was something i wanted in 0.3
<_whitenotifier-f>
[nmigen] whitequark closed issue #519: Xilinx Zynq: generated bitstreams do not work with (recent?) FPGA Manager - https://git.io/JT7pG
<lkcl>
i implemented DMI (which is a very similar protocol to how SRAMs operate) which might be a suitable candidate for the inter-CSR communication, is why i ask
<lkcl>
it's a lot simpler than wishbone.
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<jfng>
lkcl: i haven't been working on nmigen-soc for the past month due to lack of time, sorry
<whitequark>
it's not such a bad thing in the grand scheme of things as it leaves me a bit more time to finish cxxsim
<whitequark>
speaking of which, i'm currently implementing the $display cell in yosys
<lkcl>
jfng: no problem, that's good to hear as well
<lkcl>
whitequark: niiice. the MMU and I/D cache code is such a complex FSM (ported from microwatt) that we can't do without $display / Display() and have a "try import except ImportError" wrapper around Display at the moment
<lkcl>
(whitequark, translation: i'm saying thank you :) )
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<jfng>
does the encoding of FSM states belong to the public API ? (i.e. can I write code that depends on it ?)
<whitequark>
jfng: very much no at the moment
<whitequark>
but it is planned to be more user-exposed than it is now after the FSM rework that me and awygle want to do
<jfng>
okay, i'll avoid depending on it in the meantime
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<awygle>
pyrope is gonna confuse somebody when they go looking for a data structure for text
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<whitequark>
yep
<awygle>
new rule, all package names are a 6-digit base-36 number
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<agg>
is there anything public about pyrope except that one presentation from 2018?
<agg>
it seems like they maybe have https://pypi.org/project/pyrope though it points to a 404'd github repo and is an empty package
<agg>
github finds some people with pyrope syntax files in their vim config and a treesitter parser for it even
<agg>
it seems a shame to use # as the 'register' operator and then use a syntax highlighter that treats it as a comment, but maybe that's why they're writing vim syntax files :p
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<EmilJ>
awygle: what did you mean by the text data structure thing? Isn't it, like, an HDL that doesn't need strings?
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<d1b2>
<OmniTechnoMancer> A rope is a text data structure, py is a common prefix for making a python thing, so one may assume a pyrope were a python impl of the rope data structure
<EmilJ>
oh! Thank you
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<_whitenotifier-f>
[nmigen] Ravenslofty opened issue #525: [RFC] Add InstanceResource to use Instance I/O as Platform I/O - https://git.io/JTbXD
<Lofty>
Crappy RFC is crappy, but whatever
<Lofty>
Here you go, kbeckmann
<kbeckmann>
oh, thanks.
<kbeckmann>
i'm currently struggling trying to create an instance of the altera_int_osc IP
<kbeckmann>
or is this one of those encrypted IPs that i have to generate and include somehow?
<kbeckmann>
(for context, i am trying to create an instance of the internal oscillator in a Cyclon V design)
<kbeckmann>
hm is there any examples for how to generate "megafunctions" on the fly in nMigen + quartus? in this case i think i need to generate a altera_int_osc megafunction, include it in the design and create an instance of it
<kbeckmann>
i am probably doing something very wrong but i'm not sure what :)
<Lofty>
Hmm
<Lofty>
How about `cyclonev_oscillator`?
<kbeckmann>
i did like this m.submodules.intosc = Instance("altera_int_osc", i_oscena = Const(1), o_clkout = ClockSignal("intosc"))
<Lofty>
Yep
<Lofty>
Try replacing `altera_int_osc` with `cyclonev_oscillator`
<kbeckmann>
magic! i have a blinky
<kbeckmann>
thanks so much..
<Lofty>
Yet another secret of Mistral :P
<kbeckmann>
how did you find cyclonev_oscillator ?
<Lofty>
I instantiated the megafunction, and asked it to also generate a third-party file
<kbeckmann>
ah nice
<Lofty>
And inside the altera_int_osc was a cyclonev_oscillator
<kbeckmann>
ohhh now i found that too
<Lofty>
Really do think all the Altera IP library cells are pain, but
<kbeckmann>
is there a way to learn the names and parameters in a sane way?
<Lofty>
Nope
<kbeckmann>
using quartus, instantiate, export, seems a bit like a pain
<kbeckmann>
i see
<Lofty>
Unless you go through the simulation library I guess
<kbeckmann>
ah
<Lofty>
They have black boxes of things
<Lofty>
Which maybe I should extract
<Lofty>
I'm curious, do you have any way of measuring the variance on the clock?
<kbeckmann>
not right now
<kbeckmann>
i could set something up though.. as in using an SDR
<kbeckmann>
i have a GPSDO and a bunch of FPGA boards,
<kbeckmann>
i guess i could tune the GPSDO to the same frequency and then measure the variance with some gateware. but i have never done that before.
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<agg>
Lofty: just curious about accuracy of the cyclone-v internal osc?
<Lofty>
Well, daveshah is, actually, but yeah
<agg>
kbeckmann: it's so annoying! i went though that same exercise to get all the SoC instance names
<agg>
like why can't they just document the underlying names...
<Lofty>
agg: I'll get there ^^;
<agg>
Lofty: I've got a de0-nano-soc and a de0-nano (cyclone iv) and a timer/counter, probably wouldn't take long
<kbeckmann>
i am sure a lot of people will be happy for that documentation!
<agg>
are there parameters to sweep or anything?
<Lofty>
Hmm, give me a bit
<kbeckmann>
there is an extra signal in the quartus generated code, .clkout1(). not sure what that is. the normal clock output is .clkout()
<Lofty>
Doesn't look like it
<Lofty>
kbeckmann: I'm wondering if it's ~clock
<kbeckmann>
ah
<Lofty>
agg: yeah, I can't find any parameters for it, but I think Quartus itself might have some that I can't find
<Lofty>
(taking a break from my computer rn)
<Lofty>
I'm expecting hell to break out over the next few hours, so it's probably best not to look at Twitter
<agg>
yea... happy to play with a timer/counter to avoid twitter, heh
<agg>
also I basically haven't touched the de0-nano-soc board since getting it as i mostly swapped to lattice fpgas after that
<Lofty>
Well, Project Mistral is doing fairly well
<Lofty>
Sarayan thinks he understands the entire bitstream
<Lofty>
Unfortunately he hasn't written any documentation on it yet, so *I* don't :P
<agg>
hah
<agg>
everything I hear about the xilinx SoCs sounds pretty terrible whereas I mostly found the altera ones pretty ok once i found the magic instance names
<agg>
haven't tried anything since like 2017 or something though
<Lofty>
The way I'm probably going to go with the Intel flow is to define a mutually intelligible subset of modules which doesn't go through monstrosities like altsyncram or altera_pll
<Lofty>
To be fair even the native modules are a bit of a mess, but it's this or break compatibility externally
<agg>
incredible, i found 'soc.py' from dec 2017 and ran it and now the led is flashing on the de0-nano-soc
<Lofty>
Huh, wow
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<agg>
sadly it looks like nmigen-boards never got a de0-nano-soc board
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<Lofty>
Yet
<kbeckmann>
Lofty: the frequency seems to be 100MHz
<Lofty>
Huh. It's part of the bitstream config, as I understand it
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<agg>
84.5MHz here, if I just instantiate the cyclonev_oscillator
<kbeckmann>
oh ok
<kbeckmann>
it was at least not 12.5
<kbeckmann>
let me measure more precisely
<agg>
no apparent complaints from quartus
<agg>
these gpio headers were not meant to see 84MHz, the ringing is insane