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<lsneff>
When simulating my project, I'm getting `ValueError: Value (128) not representable in 7 bits` when it's in the `sim.write_vcd` function. The trace isn't particularly useful. Is there any way I can narrow down where this error is coming from?
<lsneff>
Ah, nvm, was trying to pack a value to large into a memory
<whitequark>
can you produce an MCVE? this seems like a really bad error
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<d1b2>
<OmniTechnoMancer> seems like something should have complained earlier than that?
<whitequark>
yeah
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<korken89>
When using nMigen, are there any examples on how to interoperate with litex modules? I was thinking of putting a DRAM on the board I am making to tryout the ECP5, but I don't feel like writing a DRAM controller :)
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<lsneff>
whitequark: sure will do tomorrow if I have time. Some formatting code deep in the vcd writing module was throwing, but it probably should be caught in nmigen itself.
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<d1b2>
<NZSmartie> Hi, not sure if this is on topic. the LimeSDR Mini has a Intel Max 10 FPGA, would it be okay to add a LimeSDR Mini to the nmigen-boards repo? if that's the right place to add it?
<d1b2>
<NZSmartie> (disclaimer, I haven't touched FPGAs before, and i'm trying to figure out if a LimeSDR mini is an okay place to start)
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<whitequark>
it's a reasonable addition
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<agg>
korken89: probably the simplest way at the moment is to build litedram into a verilog module, then you can use it with `platform.add_file("...")` and the `Instance` class
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<korken89>
Thanks for the tip agg!
<agg>
korken89: if you're using the rest of litex, it might be simpler to compile your nmigen designs into verilog and have litex link them in, I guess
<Shari2_>
How does one mark a subsignal as double data rate/xdr=2? I only found platfrom.request with xdr argument but the resource is already requested. I want to output a clock signal and Spartan6 wants an ODDR buffer to output a BUFG clock.
<korken89>
agg: Makes sense, I've never used litex before, but their DRAM support is what is quite interesting for me, and what I mainly used the vendor tools for before. You know, I simply want a high bandwidth bus for a DSP pipeline and DRAM fits the bill for the required bandwidth :)
<agg>
Shari2_: you have to set xdr=2 when you first request it, not afterwards, and then the thing returned from request() has a .o0, .o1, and .o_clk attribute instead of just .o
<agg>
(but I don't know about the xilinx platform stuff)
<agg>
korken89: if you do just want a standalone dram and not a whole SoC you should be ok to use litedram by itself in nmigen (after building to verilog), though i've not tried it
<korken89>
Thanks daveshah! I'll give it a try!
<korken89>
Then I feel safe about adding a DRAM module to the test board
<korken89>
A quick look seems to suggest that they generate a Wishbone interface to the controller, so that's perfect
<agg>
depending on how much bandwidth you need the hyperram stuff looks much simpler to route and control, but it's definitely not as quick as ddr3 or whatever
<daveshah>
There is also RPC coming on the horizon, but litedram support isn't quite there yet and availability is still a bit meh
<daveshah>
near-DDR3-bandwidth with far fewer pins
<agg>
and such small packages
<korken89>
I've used HyperRAM before, and it is actually OK, the issue is that DRAM is cheaper :)
<agg>
yep fair!
<korken89>
For RPC DRAM, I am quite hoping it will come more
<Shari2_>
agg: the xdr part is Spartan6/platfrom specific and the request is done by a platform independent module. I guess manualy instatiate a ODDR then?
<korken89>
I never need the density of a DRAM, like the image processing pipline I am porting now needs about 5 MB of RAM, and RPC would give me DRAM with a lot less IO and less board space
<agg>
Shari2_: a platform independent module is calling platform.request()?
<Shari2_>
agg: yes i have luna simple_device.py which calls "bus = platform.request(platform.default_usb_connection)".
<agg>
hmm, that sounds sort of trickier
<agg>
maybe ktemkin will have ideas when she's around
<ktemkin>
what’s the question?
<ktemkin>
oh, I might see
<vup>
Shari2_: you can give platform.request() a dict for xdr: `xdr = {"subsignal": 2}`, is that what you need? It should then use a ODDR on Spartan6
<vup>
oh no I misunderstood, sorry
<Shari2_>
ktemkin: I need the ulpi clock to be and output my platform (Spartan6) and to output a BUFG clock a ODRR is needed. So the question is how and where to set the xdr attribute for ulpi clk.
<ktemkin>
check out the Genesys2 platform in LUNA for an example of custom clocking that works with the default examples
<ktemkin>
I suspect you can use that construct to split the clock domain in a way that works with the examples
<ktemkin>
otherwise, add handle_clocking=False to the USBDevice instantiation, and then use xdr={‘clk’: 2} in your .request to create the DDR buffer
<ktemkin>
and then drive the signal yourself
<ktemkin>
the latter is what you want for real usage on a platform like that
<ktemkin>
but it’ll require you to tweak each example you want to use
<Shari2_>
I will try to keep platform specific parts out of generic modules. Thanks.
<ktemkin>
I mean, top-level modules maybe shouldn’t be considered necessarily generic; I just have them genericized in LUNA to make it easy to run the examples on whatever platform :)
<ktemkin>
there’s already some hacks (.request_optional) in place that make that work that you may not want to take to extremes outside of the examples
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<gerni>
Hi, is there a simple way to run nmigen-soc / minerva / lambdasoc in a simulator?I would like to take nmigen based RISC-V, write a simple "Hello World" app. in C or nim,run it all in a simulator (iverilog?). It would be nice to have the SoC serial output ("Hello World") in my terminal.
<awygle>
nmigen has an integrated simulator called pysim. it's probably a bit slow for this use case. in the relatively near future it will also have cxxsim which is intended to scale better.
<gerni>
I'm just starting so I'm looking for something simple, easy to follow, I've just tried Litex "lxsim --cpu-type=minerva", it works but ...a lot of things are happening behind, I was hoping to find something simpler
<gerni>
@whitequark wow worked out of the box, exactly what I was looking for, thanks!
<cr1901_modern>
Random musing: The ability to have multiple processes in pysim (and cxxsim? Haven't tried) is extremely useful for arranging disjoint parts of a simulation. But it seems like it would be rather easy to have multiple processes go out of sync with each other.
<cr1901_modern>
Haven't experienced this yet, but I dread the day when it happens
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<Sarayan>
You have to synchronize on the clock(s)
<Sarayan>
not sure how much the overhead would be
<Sarayan>
but I'm pretty sure the FF give you enough independant domains to make boundary-on-FF viable
<Sarayan>
just have to be careful with syncs and caches
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<lkcl>
whitequark: that minerva example is *really* useful! things like it are completely missing from nmigen-soc. working out how nmigen-soc (etc) hang together from the APIs, well-written as they are, is almost impossible.
* lkcl
makes a note of that example
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<kbeckmann>
oh, that was neat. no fuzz, it just works as well without any complicated setup.
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<kbeckmann>
i have ran into a new problem with the gowin pnr tool... when creating instances of IOBUF and TBUFs, you have to pass the actual top level port - it seems you can't have them connected through wires at all. nmigen seems to create wires even in the simplest design. is there any way to work around this?
<daveshah>
opt_clean -purge on the Yosys side might fix this, although would also be a bit of a sledgehammer
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<kbeckmann>
oh, thanks, i will try this
<kbeckmann>
it seems you can create the IOBUF instances in deeper modules, however the port has to be passed directly from module to module, not via a wire.
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<kbeckmann>
daveshah: thanks, that worked!
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