ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting November 23th
<_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jk2i6
<_whitenotifier-f> [YoWASP/yosys] whitequark d9ac9a1 - Update dependencies.
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<lsneff> Does anyone here have an example of picorv32 working with nmigen? I'm trying to get it to work, but it's pretty difficult to debug since nmigen can't simulate a verilog file.
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<whitequark> not yet :)
<whitequark> as in, can't simulate a verilog file yet. soon, though, it will
<cr1901_modern> cxxrtl to the rescue?
<whitequark> yeah
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #432: Add support for Display in simulation - https://git.io/JkV0S
<_whitenotifier-f> [nmigen] whitequark commented on issue #432: Add support for Display in simulation - https://git.io/JkV0h
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #432: Add support for Display in simulation - https://git.io/JkVEX
<lsneff> whitequark: do you know roughly when that might land?
<whitequark> several weeks
<whitequark> somewhere between the end of november and end of december it should get usable
<_whitenotifier-f> [nmigen] RobertBaruch opened issue #548: Unusual code in Operator for << and >> - https://git.io/JkVay
<lsneff> oh awesome, that's pretty soon
<lsneff> I'll probably port over to verilog until then and then port back when it releases
<_whitenotifier-f> [nmigen] whitequark commented on issue #548: Unusual code in Operator for << and >> - https://git.io/JkVre
<whitequark> port over?
<lsneff> Well, like port my hardware description that uses nmigen over to verilog
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JkVoe
<_whitenotifier-f> [nmigen/nmigen] whitequark 39ff720 - hdl.ast: remove dead code. NFC.
<whitequark> ah! you could also use picorv32 as an instance
<whitequark> and simulate the complete design with iverilog or verilator
<whitequark> (or even cxxrtl!)
<lsneff> Oh, like compile the whole thing to verilog and the simulate?
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JkVoU
<_whitenotifier-f> [nmigen/nmigen] whitequark 2ba824f - Deploying to gh-pages from @ 39ff7203ba3a511d3f4355e40fcb7249674c23e5 🚀
<lsneff> I am using picorv32 as an instance, i assumed that couldn't be simulated with pysim
<whitequark> yeah, but you could ditch pysim instead of ditching nmigen
<_whitenotifier-f> [nmigen] RobertBaruch closed issue #548: Unusual code in Operator for << and >> - https://git.io/JkVay
<lsneff> I definitely don't want to pitch nmigen, I guess I didn't realize there were alternatives before cxxsim lands!
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #539: [RFC] Clarify the meaning of Past and friends when there is no lexically enclosing scope - https://git.io/JkVoy
<_whitenotifier-f> [nmigen] whitequark commented on issue #548: Unusual code in Operator for << and >> - https://git.io/JkVoN
<_whitenotifier-f> [nmigen] whitequark closed issue #539: [RFC] Clarify the meaning of Past and friends when there is no lexically enclosing scope - https://git.io/Jkfm4
<lsneff> Oops, *don't want to ditch
<_whitenotifier-f> [nmigen] cestrauss commented on issue #539: [RFC] Clarify the meaning of Past and friends when there is no lexically enclosing scope - https://git.io/JkV6Z
<_whitenotifier-f> [nmigen] cestrauss edited a comment on issue #539: [RFC] Clarify the meaning of Past and friends when there is no lexically enclosing scope - https://git.io/JkfOM
<_whitenotifier-f> [nmigen] cestrauss edited issue #539: [RFC] Clarify the meaning of Past and friends when there is no lexically enclosing scope - https://git.io/Jkfm4
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<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #548: Unusual code in Operator for << and >> - https://git.io/JkVNd
<_whitenotifier-f> [nmigen] RobertBaruch edited a comment on issue #548: Unusual code in Operator for << and >> - https://git.io/JkVNd
<_whitenotifier-f> [nmigen] RobertBaruch edited a comment on issue #548: Unusual code in Operator for << and >> - https://git.io/JkVNd
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<lkcl> lsneff: litex automatically compiles and uploads picorv32 to every single one of the supported FPGAs with a single command.
<lkcl> it is also possible to compile and run picorv32 by way of verilator simulation... with a single litex command.
<lkcl> _florent_ very kindly spent the time to help us get LibreSOC compilation for ECP5 and verilator simulation into litex as well.
<lkcl> LibreSOC is written in nmigen... and yet, by compiling to verilog, can be re-imported by litex and compiled for running under verilator...
<lsneff> Hmm, maybe I should actually just write a basic riscv cpu in nmigen instead. Would be a good learning experience
<vup> there is also atleast one risc-v cpu in nmigen: https://github.com/lambdaconcept/minerva
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<_whitenotifier-f> [nmigen] vmunoz82 opened issue #549: XilinxSpartan6Platform and XilinxSpartan3APlatform support broken on commit 2f8669ca - https://git.io/Jkwmo