<d1b2>
<OmniTechnoMancer> need to get it to map to LUT ram 😛
<whitequark>
i think logic cells in commercial FPGAs are typically laid out by hand
<d1b2>
<OmniTechnoMancer> most likely
<d1b2>
<OmniTechnoMancer> but if doing an FPGA in an FPGA you can probably abuse the distributed RAM to let you program the LUT
<whitequark>
oh right i see what you meant
<whitequark>
totally lost the context for a moment, sorry
electronic_eel has quit [Ping timeout: 240 seconds]
electronic_eel has joined #nmigen
PyroPeter_ has joined #nmigen
PyroPeter has quit [Ping timeout: 272 seconds]
PyroPeter_ is now known as PyroPeter
phire has quit [Remote host closed the connection]
phire has joined #nmigen
_whitelogger has joined #nmigen
emeb_mac has quit [Quit: Leaving.]
_whitelogger has joined #nmigen
_whitelogger has joined #nmigen
jjeanthom has joined #nmigen
electronic_eel_ has joined #nmigen
electronic_eel has quit [Ping timeout: 256 seconds]
mogery has joined #nmigen
electronic_eel_ is now known as electronic_eel
<mogery>
so i made something like this: https://dpaste.com/AY73J4WNC and when i run the simulator i only see the wave of "a.a" in gtkwave
<mogery>
how can i make the simulator display all of the as?
<mogery>
oh, right. i need m.submodules, nevermind
<asu>
you probably got an unused elaboratable warning, right?
<asu>
i also got confused by the same thing once and i didn't really pay close attetion to the warning
<mogery>
yup, i did
jjeanthom has quit [Ping timeout: 264 seconds]
<lkcl>
mogery: about what jeanthom said yesterday, yes i use yosys "read_ilang {filename}" followed by "show {insert modulename which defaults to top}" a _lot_
<lkcl>
you need graphviz and xdot installed.
<lkcl>
if you want it to generate pdf or svg check how with "help show" in yosys
<lkcl>
a useful clue that you'd missed out the "m.submodules +..." was missing would have been that, in the visual graph, the submodule instance would have been entirely missing
<lkcl>
the graphs i've found to be an extremely important understanding and sanity-checking of any given design
<lkcl>
consequently i set myself a rule, "if i can't understand it or read it on graphviz it's not been subdivided into small enough submodules"
<whitequark>
i mean or you could look for the warning...
<whitequark>
it's true that our diagnostics kind of suck
<whitequark>
fortunately, newer python (than we support...) has writable .tb_next
<whitequark>
we can't polyfill it on 3.6, but we can start integrating with python's native backtraces on 3.7+
<whitequark>
mostly useful for simulation, of course. pretty fast on cxxrtl :)
<d1b2>
<TiltMeSenpai> does nmigen have a way to annotate multi-cycle processes?
<d1b2>
<TiltMeSenpai> actually can yosys/nextpnr handle them?
<whitequark>
nope, too low-level for that
<whitequark>
either of these tools
<d1b2>
<TiltMeSenpai> ah, ok
<d1b2>
<TiltMeSenpai> so you would probably go sync -> sync and just manually verify that the failed timing looks about right?
<whitequark>
hang on
<whitequark>
*those* multicycle processes
<whitequark>
i was thinking of something entirely different and irrelevant
<whitequark>
ok, so nmigen and yosys don't necessarily care
<whitequark>
as far as i'm concerned, a multicycle process is just a clock domain with a related clock
<whitequark>
it would be mostly on nextpnr to support that
<d1b2>
<TiltMeSenpai> ah, ok. Not planning on doing that any time soon, so it's not super concerning to me, but I'm just curious
<mogery>
if i do abs(self.a.as_signed()) // abs(self.b.as_signed()) it still thinks it's a signed value and errors out on me
<mogery>
abs(self.a.as_signed()).as_unsigned() // abs(self.b.as_signed()).as_unsigned() doesn't work because "AttributeError: 'Operator' object has no attribute 'as_unsinged'"
<lsneff>
asu: I haven't decided yet. Imgui would be fine, iced is also a good choice.
<whitequark>
"as_unsinged" should be "as_unsigned". typo.
<mogery>
:facepalm:
emeb_mac has joined #nmigen
nelgau has joined #nmigen
jjeanthom has joined #nmigen
mogery has quit [Read error: Connection reset by peer]