ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting November 9th
<lkcl> awygle: thank you. well it's that we've now got a large codebase (68,000 up from 45,000 for the core, 26,000 for the IEEE754 FP library) and so a code-morph is a little bigger than it would be for e.g. a 4,000 line project.
<_whitenotifier-f> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JTp2g
<_whitenotifier-f> [YoWASP/nextpnr] whitequark 495558f - Update dependencies.
<awygle> yup, understood
<lkcl> so a migration path is real handy
<_whitenotifier-f> [nmigen] whitequark commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTp21
<awygle> to be clear the branch above should have no functional change compared to Record as it is now
<whitequark> what awygle did *is* a migration path
<whitequark> (if i correctly recall the PR we discussed)
<lkcl> ah super
<awygle> yup. NFC, but record is based on ValueCastable not UserValue (which i guess could have functional changes if you're doing something particularly weird, but that's why testing)
<lkcl> hm, i wonder, awygle, if you'd like some $EUR for doing that? would that help at all?
<awygle> i'm financially pretty ok, and i don't live in the EU so the logistics are not straightforward
<lkcl> very few of us do, and it's not a problem.
<lkcl> however if you're financially doing ok then great
<lkcl> NLnet is very flexible, you don't have to *live* in the UK. only the person who signs the MoU has to list an *address* that is in the EEC. which includes Iceland. which we have someone whose home address is there :)
<lkcl> s/UK/EU
<awygle> a sad correction
<whitequark> awygle: > object.__new__ and object.__init__ are special in another way. For the object class itself, their signatures are (Subclass[T]) -> T and (T) -> None. However, when called from subclass constructors via super(), the signatures are (Subclass[T], *args, **kwargs) -> T and (T, *args, **kwargs) -> None.
<whitequark> wtf
<awygle> oh python. you never stop giving.
<lkcl> ahh you're overriding __new__ and __init__? oooo
<lkcl> i know someone who knows how they work
<whitequark> not __init__. only __new__
<lkcl> 1 sec
<awygle> doesn't that mean it should _want_ me to do the *args, **kwargs thing?
<whitequark> i know how they work in general
<awygle> but i got a syntax error
<lkcl> i got advice from them on stackexchange, i was really amazed and delighted
<whitequark> what i'm currently looking at is a particularly subtle corner case
<lkcl> i've done mro / base stuff before, what's the case?
<whitequark> this is hella cursed
<awygle> whoof.
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #449 commit - https://git.io/JTpaq
<awygle> yeah i agree with that conclusion (and take a shot of my python whiskey)
<awygle> our MSPV is 3.6 right?
<awygle> because my Record migration uses callable() which is missing from exactly and only 3.0 and 3.1
<whitequark> yup
<whitequark> py3k before 3.4 basically never mattered to anyone
<whitequark> unusable
<awygle> mhm
<_whitenotifier-f> [nmigen] whitequark closed pull request #449: Implement ValueCastable - https://git.io/JJ8yx
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JTpa4
<_whitenotifier-f> [nmigen/nmigen] awygle 06c7349 - hdl.ast: implement ValueCastable.
<_whitenotifier-f> [nmigen] whitequark closed issue #355: [RFC] Redesign UserValue to avoid breaking code that inherits from it - https://git.io/Jfeyi
<awygle> hm that RFC has us deprecating UserValue in 0.3, is that still the plan?
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpau
<_whitenotifier-f> [nmigen/nmigen] whitequark 85e9a3c - Deploying to gh-pages from @ 06c734992fd46b6f11bdfa4425ef102640aecf3f 🚀
<whitequark> yes
<_whitenotifier-f> [nmigen] whitequark opened issue #527: Deprecate UserValue - https://git.io/JTpaz
<_whitenotifier-f> [nmigen] whitequark edited issue #527: Deprecate UserValue - https://git.io/JTpaz
<_whitenotifier-f> [nmigen] whitequark opened issue #528: Redesign Record to be based on ValueCastable - https://git.io/JTpay
<_whitenotifier-f> [nmigen] awygle opened pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<awygle> goddamit git and/or github
<whitequark> agh
<whitequark> i even wondered if you were typing that one, then decided you'd probably say
<_whitenotifier-f> [nmigen] awygle synchronize pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<whitequark> wait
<whitequark> that's a PR not an issue
<awygle> correct
<awygle> it even references the issue
<awygle> i just pushed wrong because push doesn't work on your checked out branch if you specify a remote and a remote branch but i always think it will
<awygle> fixed now
<whitequark> fastest implementation of *any* feature i've ever seen :p
<awygle> that's what we in the biz call "cheating" :p
<whitequark> 2 minutes from issue to PR :p
<_whitenotifier-f> [nmigen] codecov[bot] commented on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<awygle> is codecov updating while the CI is still running? that seems... not right.
<awygle> (i know, i know, just ignore codecov... but i can't apparently)
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<whitequark> awygle: several CI jobs
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpVi
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpVP
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpVX
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpV1
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpVM
<_whitenotifier-f> [nmigen] awygle reviewed pull request #529 commit - https://git.io/JTpVj
<_whitenotifier-f> [nmigen] awygle synchronize pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] awygle synchronize pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpwW
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #529 commit - https://git.io/JTpwu
<_whitenotifier-f> [nmigen] awygle reviewed pull request #529 commit - https://git.io/JTpwg
<_whitenotifier-f> [nmigen] awygle synchronize pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<awygle> whitequark: can you take the deprecation of UserValue? i'm not totally sure how you want that done
<whitequark> awygle: taken
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<awygle> sweet, thx
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] whitequark commented on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpw5
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpVv
<_whitenotifier-f> [nmigen] awygle commented on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTprU
<_whitenotifier-f> [nmigen] whitequark commented on pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTprI
<_whitenotifier-f> [nmigen] whitequark closed issue #528: Redesign Record to be based on ValueCastable - https://git.io/JTpay
<_whitenotifier-f> [nmigen] whitequark closed pull request #529: Migrate Record to ValueCastable, from UserValue - https://git.io/JTpad
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JTprq
<_whitenotifier-f> [nmigen/nmigen] awygle abbebf8 - hdl.rec: migrate Record from UserValue to ValueCastable.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTprY
<_whitenotifier-f> [nmigen/nmigen] whitequark 59b7db1 - Deploying to gh-pages from @ abbebf8efe931938f0de95d041f1d91c693efddc 🚀
<awygle> oh i was gonna PR that thing from harmon
<awygle> ... maybe after dinner
<whitequark> awygle: excellent work
<whitequark> makes us materially closer to release
* awygle waves hands, makes "pshaw" noises
<awygle> happy to help
<awygle> we're just waiting on cxxsim now right? well and the deprecation which shouldn't take long
<whitequark> two things, merging cxxsim and Display (which is cxxsim-adjacent)
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTprK
<awygle> anything i can do to help with either of those?
<whitequark> possibly but i'll need to dig deeper into ... both of them really
<awygle> (they seem pretty far in your wheelhouse but)
<awygle> mk, lmk, i'll run off and work on other stuff til i hear from you i spose :p
<whitequark> Display is mostly just annoying yosys plumbing
<whitequark> cxxsim might or might not require new creative additions to the C API
<awygle> mmm C APIs, my favorite
<whitequark> cxxrtl's is explicitly designed to be easy to bind from rust
<whitequark> carefully chosen ownership
<awygle> that's cool. though i have a hard time imaginging a use case where rust would bind cxxrtl instead of writing rsrtl, being careful about ownership is always a good thing lol
<whitequark> well, cxxrtl has C++ blackboxes
<whitequark> maybe you want to link those
<awygle> True
<_whitenotifier-f> [nmigen] whitequark commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTprF
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JTpow
<_whitenotifier-f> [nmigen/nmigen] whitequark c6150d0 - vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpoK
<_whitenotifier-f> [nmigen/nmigen] whitequark 3d51bf6 - Deploying to gh-pages from @ c6150d05867bea1a7266e3c950d3d9846ba7ed58 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JTpox
<_whitenotifier-f> [nmigen/nmigen] whitequark 10fd5cf - CI: run testsuite with -Werror.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpKf
<_whitenotifier-f> [nmigen/nmigen] whitequark 33cdac0 - Deploying to gh-pages from @ 10fd5cff4ba3f6715146947c67c1a84e28926b10 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/JTpKZ
<_whitenotifier-f> [nmigen/nmigen] whitequark db5a981 - CI: add CPython 3.9 to test matrix.
<_whitenotifier-f> [nmigen/nmigen] whitequark 8313d6e - cli: update deprecated import.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpKc
<_whitenotifier-f> [nmigen/nmigen] whitequark 17b3912 - Deploying to gh-pages from @ 8313d6e71cfe758748707b37bf6745b19fb6c62a 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 2 commits to master [+0/-0/±5] https://git.io/JTpK5
<_whitenotifier-f> [nmigen/nmigen] whitequark bb6a233 - Fix commit 8313d6e7.
<_whitenotifier-f> [nmigen/nmigen] whitequark 6e7dbe0 - examples: clean up oudated code.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpKA
<_whitenotifier-f> [nmigen/nmigen] whitequark 44caa38 - Deploying to gh-pages from @ 6e7dbe004e5aa3ebb165e5c0a4ce05108668f664 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JTp6D
<_whitenotifier-f> [nmigen/nmigen] whitequark c9fd000 - sim.pysim: avoid redundant VCD updates.
<_whitenotifier-f> [nmigen] whitequark closed issue #429: values in vcd are zero despite simulation's nonzero values - https://git.io/JJYIO
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTp69
<_whitenotifier-f> [nmigen/nmigen] whitequark 89e1b3d - Deploying to gh-pages from @ c9fd00010315d5ee12bd35c54176d9b1836e1749 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/JTpiz
<_whitenotifier-f> [nmigen/nmigen] whitequark bde37fe - hdl.ast: deprecate UserValue in favor of ValueCastable.
<_whitenotifier-f> [nmigen] whitequark closed issue #527: Deprecate UserValue - https://git.io/JTpaz
<whitequark> okay, there are just 3 milestone issues left https://github.com/nmigen/nmigen/milestone/3
<whitequark> basically all cxxrtl related
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTpi2
<_whitenotifier-f> [nmigen/nmigen] whitequark b2921b7 - Deploying to gh-pages from @ bde37fe2f2eb83a950f9a1beefca888c3fede3f2 🚀
<cr1901_modern> whitequark: I haven't been following #526 closely, but re: $global_clock I thought the proposed idea was to automatically derive a set of assumes so that each clock eventually ticks (thus not exposing $global_clock at all)
<cr1901_modern> at all in nmigen*
<whitequark> right, that was long enoough ago i forgot about it
<whitequark> that's also reasonable
<whitequark> you need basically one $ff cell instantiated by the platform
<whitequark> then assume(xor(ff.q,ff.d))
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<cr1901_modern> That wasn't how I did such assumes- I did it the naive way (assume (clk0_prev != clk0) or (clk1_prev != clk1));... something like that) but that sounds like it would work too.
<_whitenotifier-f> [nmigen] whitequark commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTpPU
<_whitenotifier-f> [nmigen] whitequark edited a comment on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTpPU
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<cr1901_modern> God I'm scatterbrained tonight
<cr1901_modern> https://github.com/cr1901/spi_tb/blob/master/spi_tb.v#L78-L81 Yea, this is what I did... somewhere in our privmsgs we fleshed out how to extend it to more clocks. But this is enough for tonight :P.
<d1b2> <OmniTechnoMancer> Is there any guidance on how one does assumes to assume that the reset has been asserted at the beginning of modeling and released!
<d1b2> <OmniTechnoMancer> ?
<cr1901_modern> something like "initial assume rst == 1" should be enough.
<d1b2> <OmniTechnoMancer> Ah cool, or 0 if active low reset I assume
<cr1901_modern> indeed
<awygle> If you're doing K-induction that will only work for BMC
<cr1901_modern> I admit I'm not gonna work out an example on paper/in my head tonight, but if you're reset is working properly, the lack of "initial assume rst == 1" shouldn't screw up the proof.
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTpQm
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<d1b2> <OmniTechnoMancer> For k-induction or BMC or both?
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<cr1901_modern> for k-induction; initials work with BMC
<cr1901_modern> but they're not meaningful for k-induction
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<d1b2> <OmniTechnoMancer> I see
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<_whitenotifier-f> [nmigen-boards] kbeckmann opened pull request #119: Add Chameleon96 - https://git.io/JThUf
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<_whitenotifier-f> [nmigen-boards] kbeckmann opened pull request #120: ci: Install nMigen from git - https://git.io/JThTH
<_whitenotifier-f> [nmigen-boards] kbeckmann edited pull request #120: ci: Install nMigen from git - https://git.io/JThTH
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<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #120: ci: Install nMigen from git - https://git.io/JThCO
<_whitenotifier-f> [nmigen-boards] whitequark closed pull request #120: ci: Install nMigen from git - https://git.io/JThTH
<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #119 commit - https://git.io/JThC8
<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #119 commit - https://git.io/JThCB
<_whitenotifier-f> [nmigen-boards] kbeckmann reviewed pull request #119 commit - https://git.io/JThWg
<_whitenotifier-f> [nmigen-boards] kbeckmann reviewed pull request #119 commit - https://git.io/JThWK
<cesar[m]> whitequark: In the VCD file generated by cxxsim, there is no "top" module, like in pysim.
<cesar[m]> This means I can't use the same GTKWave document for both.
<cesar[m]> Also, enum traces are not supported (the numerical values are recorded instead).
<cesar[m]> Also, there are a couple of FIXMEs in write_vcd (write the gtkw file and use the traces parameter).
<cesar[m]> Are these on your radar?
<whitequark> cesar[m]: well... sure? i put the FIXMEs there and the branch is not merged yet because of issues like that
<whitequark> i think we can track them in an issue, feel free to comment on GH and I'll put them in a task list
<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #119 commit - https://git.io/JThlX
<_whitenotifier-f> [nmigen] whitequark commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JTh8Y
<_whitenotifier-f> [nmigen] cestrauss commented on issue #324: Integrate cxxrtl simulator - https://git.io/JTh8F
<cesar[m]> Thanks, just checking.
<_whitenotifier-f> [nmigen] kbeckmann opened pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0s
<_whitenotifier-f> [nmigen] codecov[bot] commented on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen-boards] kbeckmann synchronize pull request #119: Add Chameleon96 - https://git.io/JThUf
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #530 commit - https://git.io/JThEc
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #530 commit - https://git.io/JThEC
<_whitenotifier-f> [nmigen] kbeckmann synchronize pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0s
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] kbeckmann reviewed pull request #530 commit - https://git.io/JThEM
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] codecov[bot] edited a comment on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0r
<_whitenotifier-f> [nmigen] whitequark closed pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JTh0s
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JThu4
<_whitenotifier-f> [nmigen/nmigen] kbeckmann ebbdac9 - vendor.intel: add support for Cyclone V internal oscillator
<_whitenotifier-f> [nmigen] whitequark commented on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JThuR
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JThuu
<_whitenotifier-f> [nmigen/nmigen] whitequark bcc0bba - Deploying to gh-pages from @ ebbdac97987cb91e2418e80e2416c3a81f1dabdc 🚀
<_whitenotifier-f> [nmigen] kbeckmann commented on pull request #530: intel: Add support for Cyclone V internal oscillator - https://git.io/JThuj
<d1b2> <dub_dub_11> Woo just tested my board definition file for the de1 soc
<d1b2> <dub_dub_11> Runs the blinky test from nmigen-boards
<whitequark> \o/
<_whitenotifier-f> [nmigen-boards] kbeckmann reviewed pull request #119 commit - https://git.io/JThgU
<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #119 commit - https://git.io/JThg8
<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #119 commit - https://git.io/JThg4
<d1b2> <dub_dub_11> Ah
<d1b2> <dub_dub_11> I don't think I've correctly got the setup going though
<d1b2> <dub_dub_11> Because running python de1_soc is fine but I can't import it
<d1b2> <dub_dub_11> And it doesn't appear in package contents when I do help(nmigen_boards)
<whitequark> what happens when you do `import nmigen_boards.de1_soc`?
<d1b2> <dub_dub_11> No module named de1_soc
<whitequark> hmmm
<whitequark> where did you put it?
<d1b2> <dub_dub_11> Not certain cause I used pip
<whitequark> what pip command did you use?
<d1b2> <dub_dub_11> Think it was pip install git+URL.git#egg=add-de1-soc
<d1b2> <dub_dub_11> add-de1-soc is the branch name
<whitequark> `pip install git+URL.git@add-de1-soc#egg=nmigen-boards` should be the right one
<d1b2> <dub_dub_11> Ahh
<d1b2> <dub_dub_11> Okay
<d1b2> <dub_dub_11> I will try that
<d1b2> <dub_dub_11> Guess I pulled master branch then
<d1b2> <dub_dub_11> There it is
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<d1b2> <dub_dub_11> Cool I can program another design having imported the module
<d1b2> <dub_dub_11> I'll submit a PR later today to add De1-SoC then
* zignig checks that the 5V supply is working.
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate cxxrtl simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate cxxrtl simulator - https://git.io/Jv8VZ
<whitequark> cesar[m]: check out the new list in https://github.com/nmigen/nmigen/issues/324
<whitequark> that should be exhaustive now
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark opened issue #531: Implement missing CXXRTL features - https://git.io/JThSY
<_whitenotifier-f> [nmigen] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/Jv8VZ
<_whitenotifier-f> [nmigen] whitequark edited issue #531: Implement missing CXXRTL features - https://git.io/JThSY
<_whitenotifier-f> [nmigen] whitequark edited issue #531: Implement missing CXXRTL features - https://git.io/JThSY
<whitequark> since i know some people in this channel have previously experienced issues with pip: the pip developers would like to hear about those. check out https://www.ei8fdb.org/thoughts/2020/03/pip-ux-study-recruitment/
<_whitenotifier-f> [nmigen-boards] kbeckmann synchronize pull request #119: Add Chameleon96 - https://git.io/JThUf
<_whitenotifier-f> [nmigen-boards] kbeckmann reviewed pull request #119 commit - https://git.io/JThdt
<_whitenotifier-f> [nmigen] RobertBaruch commented on issue #526: Past should not be allowed in m.d.comb - https://git.io/JThFy
<cesar[m]> whitequark: The lists of cxxsim and cxxrtl tasks are very interesting and informative.
<cesar[m]> The partition among blocker and non-blocker issues is also nice.
<cesar[m]> I'll let you know if I find something not on those lists.
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<awygle> I like the phrase "systematic issues with edge-triggered logic"
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<whitequark> one bug is happenstance, two is coincidence, but three is a systematic problem
<hell__> ^
<whitequark> i could keep working around that and i know i can make the workarounds clear and documented, but maybe that's the wrong thing to do
<awygle> it's a very evocative description of the real problem
<awygle> but it is also amusing in that, read literally, it would cast doubt on the entire fabric of D-flip-flop-based digital design
<whitequark> oh lol
<awygle> "friendship over with edge-triggered logic, now level-triggered logic is my best friend"
<whitequark> i remember explaining to someone mathematically inclined how and why 2FF synchronizers work
<whitequark> "what? it still breaks, it just doesn't break often enough to care??"
<whitequark> (paraphrased)
<awygle> i was typing "oh you mean that they don't, except statistically?"
<awygle> you just have to explain to them that in the limit as n->inf an nFF synchronizer works
<awygle> "it's like a taylor expansion"
<ktemkin> friendship ended with synchronous logic; null-convention-logic is my new best friend
<whitequark> whoa, TIL
<whitequark> .. why is it trademarked
<awygle> somebody in the digital design discord was all gung-ho about null convention logic not that long ago
<whitequark> reminds me of Tri-State™
<awygle> is NCL also reversible?
<ktemkin> pretty sure the initial research was a SBIR, one of those Small Business Innovation grants from the military
<_whitenotifier-f> [nmigen] whitequark edited issue #207: Enhancing the FSM sub-language - https://git.io/JTjar
<ktemkin> which is why it's trademarked
<awygle> the math of this is very cool but as soon as they start talking about circuit implementation it feels like they went off the rails a bit