#nmigen on 2020-11-12 — irc logs at freenode.irclog.whitequark.org

2020-11-03 09:45 ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting November 9th

00:20 <awygle> whitequark: do you think that bug should be tracked for documentation purposes? seems like something that people might run into a lot

00:23 <whitequark> mm, perhaps

00:38 <awygle> or even a more focused diagnostic in add_clock_constraint

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02:51 <cr1901_modern> Is it always recommended to create new clock domains via a minimal "super"module? https://github.com/nmigen/nmigen/blob/master/examples/basic/arst.py#L18-L21

02:58 <whitequark> no; that's just an example

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05:25 <cr1901_modern> (2.5 hours late, but...) Ahh I see, just wondering. Will try moving the clock domain statements into the module and seeing what happens

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07:24 <_whitenotifier-f> [nmigen] awygle commented on issue #542: Using ClockSignal in platform.add_clock_constraint - https://git.io/Jkto7

07:25 <_whitenotifier-f> [nmigen] awygle reopened issue #542: Using ClockSignal in platform.add_clock_constraint - https://git.io/JkLmp

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17:17 <_whitenotifier-f> [nmigen-boards] kowalewskijan synchronize pull request #117: Add quickfeather board - https://git.io/JTYG0

17:17 <_whitenotifier-f> [nmigen-boards] kowalewskijan reviewed pull request #117 commit - https://git.io/JkqyD

17:21 <_whitenotifier-f> [nmigen-boards] kowalewskijan reviewed pull request #117 commit - https://git.io/JkqSk

17:22 <_whitenotifier-f> [nmigen-boards] kowalewskijan reviewed pull request #117 commit - https://git.io/JkqSG

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