Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Has any of you people found any information about some kind of "burst" capability on the clock muxes? Whatever that means?
<gatecat> never heard of anything like that before
<gatecat> sounds... cursèd
<gatecat> is there any possibility it is linked to the dqs stuff? that would involve a "burst" of clocks
<Sarayan> I'ts very possible, lemme check a thing
<Sarayan> there are 3 bits of input towards a burst counter
<Sarayan> the clk burst block has 3 bits of counter, an enable line and a clock input line, and the output is an enable signal
<Sarayan> so the burst thing is an enable shaper
<Sarayan> yep, the enable input can be use either directly or through that burst thing
<Sarayan> possibly it keeps the actual enable active for a number of clocks once it gets an edge on the line
<Sarayan> not sure how we could test that
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<Sarayan> ok, pushed a first version of the CMUXHG doc
<Sarayan> gatecat: let me know if it's understandable
<gatecat> Sarayan: thanks, I'll probably have a look at it tomorrow
<Sarayan> have fun :-)
<Sarayan> having one mostly done is going to make the others easier, I think
<Sarayan> (there are 5 different types)