<JJJollyjim>
not sure how it interacts with latexmk though
<Lofty>
Okay, built and pushed
<Sarayan>
cool
<Sarayan>
so.... that means you can FF the same lut output on two different clocks/enables
<Sarayan>
that's interesting
<Sarayan>
makes having two ffs per lut possibly more interesting
<Lofty>
Sarayan: I mean, I suspect that the only time it gets used in practice is if the same LUT is used with two different enables
<Sarayan>
Lofty: Yeah, that's pretty much the only way that makes sense in practice, even if I suspect there potentially other funky cases, like clocks with the same frequency but different phases
<gatecat>
Sarayan: in the CMUXHG diagram (for now I'm only considering the general routing inputs, a tiny bit of general routing in the clock path isn't generally a big deal to start with), do you know why CLKIN feeds both 27 and 33?
<Sarayan>
I'm not entirely convinced it makes any real sense no
<Sarayan>
you could use the direct clock pin -> cmux path
<gatecat>
yeah, they need to be added but I started with clocks from fabric because that's most general
<Sarayan>
gatecat: I kinda suspect that between the clock pin and pll counters direct links they're not that used in practice
<gatecat>
they would be useful if we want to divide a clock in fabric, which we might need for testing before plls are working
<gatecat>
but yeah, a good design and a correct PCB layout* shouldn't need them at all
<Sarayan>
Sure, but I mean eventually in real designs :-)
<Sarayan>
yeah
* gatecat
has never messed up a pcb layout and not used a correct clock pin, definitely never :p
<Sarayan>
ne-ver
<Sarayan>
I suspect wherever the clock is coming from, you want to plonk it in a pll anyway
<gatecat>
mmm
<gatecat>
I presume there is some dedicated IO to PLL routing, too ?
<Sarayan>
clock pin yes, otherwise it's the usual DCMUX
<gatecat>
right, that makes sense
<Sarayan>
there's pll-pll direct links too, to cascade them
<gatecat>
nice
<gatecat>
are these in mistral already?
<Sarayan>
Not yet
<Sarayan>
I've started studying the plls, they're interesting
<gatecat>
fun
<Sarayan>
9 counter ouputs + m, bunch of direct links all over the place
<Sarayan>
they really worked their clocks
<Sarayan>
of course, given how important they are, they better
<gatecat>
indeed
<gatecat>
are there a bunch of weird analog parameters for the PLL, too?
<Sarayan>
I don't think so
<gatecat>
good, that makes things easier
<Sarayan>
for sure
<gatecat>
lattice have them, but ecppll kinda fudges them and probably isn't giving optimum loop bandwidth in all cases