Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<Sarayan> Lofty: well, I was quite interested by the "going to bed" alternative ;-)
<Sarayan> https://app.diagrams.net/#HFPGA-fun-for-the-whole-family%2Fmistral-cyclonev%2Fmaster%2Fnotes%2Fclkmux_tb-model.dio
<Sarayan> https://app.diagrams.net/#HFPGA-fun-for-the-whole-family%2Fmistral-cyclonev%2Fmaster%2Fnotes%2Flab-model.dio
<Lofty> Well that's unusable on mobile :P
<gatecat> lol, those names look a lot like they were derived from HDL source
<Sarayan> they come from the _model.ddb files, some reduced in length (see xxx-names.txt for the actual table)
<Sarayan> that's why it's in the non-public repository
<Sarayan> that's the blocks from the point of view of the timings models
<Lofty> Interesting to note
<yorick> Sarayan: ever looked at my crashing rbf?
<yorick> also, we can donate a de0-nano-soc if it'd help
<Sarayan> yorick: I haven't yet, can you remind me?
<yorick> 14:20 <yorick> Program received signal SIGSEGV, Segmentation fault.
<yorick> 14:20 <yorick> 0x000000000040d45d in mistral::CycloneV::rbf_load (this=this@entry=0x7ffff7a16010, data=<optimized out>, size=<optimized out>) at cv-files.cc:111
<yorick> 14:20 <yorick> 111 if((d[pos >> 3] >> (pos & 7)) & 1) {
<yorick> <yorick> decrypt using your ssh key: curl https://pub.yori.cc/socfpga-2.1.rbf.age | age -d -i ~/.ssh/id_rsa - > socfpga-2.1.age
<yorick> <yorick> and I'm calling ./mistral-cv cycle 5CSEMA6U23C6 ./test-i.rbf ./test.rbf
<Sarayan> checking
<Sarayan> you're sure of your model?
<Sarayan> the low byte of your idcode is 0x01, which sx120f is 0x02
<Sarayan> (I haven't found where the high byte is yet...)
<Sarayan> it works with 5CSEMA4U23C6 (sx50f)
<yorick> hrm
<yorick> set_global_assignment -name DEVICE 5CSEMA4U23C6
<yorick> oh no :(
<yorick> sorry for wasting your time
<Sarayan> that's ok :-)
<Sarayan> is it code you have the source for?
<yorick> yeah
<yorick> but it uses qsys for a bunch of shared memory and an avalon uart+i2c bridge
<Sarayan> cool
<Sarayan> are you actually using a clock coming from the arm?
<Sarayan> I'm seeing s HPS_CLOCKS.031.060:RIGHT_CLOCK_SEL.0 2
<Sarayan> and wondering if it's right or another fuckup :-)
<Sarayan> especially since it's using weird bits in the firmware
<Sarayan> and you're using one dsp, that's cool :-)
Lofty changed the topic of #prjmistral to: Project Mistral: Yosys and nextpnr on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<Lofty> No "(and hopefully)" about nextpnr anymore :3
<Sarayan> huhuhu
<Sarayan> gatecat is doing a nice job
<Sarayan> I wonder if there's a not too expensive, cyclonev pcie card
<Sarayan> hmmm, looks like terasic is down
<gatecat> It'd certainly be nice if there was a not too expensive way of getting the 300k device
<Sarayan> 300k?
<gatecat> the '9' device, I think it is
<gatecat> 301k LEs or whatever
<Sarayan> ah, the gt300
<Sarayan> it's not required for pcie, but otoh it seems to be the only one with a devboard with pcie
<Sarayan> urgh that crap is so fucking complicated
<Sarayan> urrrrrrrrrrrrrgh
<chipb> Sarayan: speaking also as a not-spokesperson, I also feel compelled to point out that sense often doesn't match corporate reality.
<Sarayan> chipb: That very true
<chipb> hm. I suppose you're interested in exercising pcie with the tranceivers moreso than pcie-attached formfactor for application?
<Lofty> Well, having PCIe transceivers and not being able to check if they work is a bit annoying.
<chipb> indeed.
<Lofty> Having MLABs and them appearing to be broken in a subtle way is also quite annoying
* Lofty grumbles
<gatecat> have we got a similar graph for the MLAB as the LAB one you linked, Sarayan ?
<gatecat> it would be interesting to diff the two, if we can filter out the MLAB-specific stuff
<gatecat> also, it's a bit dated but one or two interesting nuggets in this paper: https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.432.6356&rep=rep1&type=pdf
<gatecat> I don't think Cyclone V has the clock borrowing, but as it's 28nm too other stuff might be similar
<chipb> ugh. I really think you might need to byob for a reasonably priced pcie-capable cv kit.
<gatecat> or just wait for good luck on eBay
<chipb> oh, I guess that too.
<gatecat> I got a ridiculous deal on two Nallatech 510Ts (two Arria 10 GX1150s each)
<gatecat> unfortunately, BittWare doesn't provide docs to second hand purchasers
<chipb> cyclone v pcie is in an odd niche.
<gatecat> so I haven't actually done anything with them other than a JTAG scan (which did at least work) so far
<gatecat> the Cyclone V with PCIe devkits on eBay are a lot less of a good deal tho :/
<chipb> huh. I do see an arria v gx kit going for $500 USD buy it now.
<gatecat> there are also the Microsoft cards available cheap
<chipb> not cheap, but perhaps of interest.
<chipb> ...microsoft cards?
<gatecat> thins like https://www.ebay.co.uk/itm/313514789194?hash=item48fef0094a:g:rm8AAOSwMFFgjliK
<gatecat> afaik some people have done some RE on them
<chipb> that one's almost certainly an A10.
<chipb> unclear to me how it ended up on the public market.
<gatecat> I think that one's a S5, but there are others with A10
<gatecat> mmm, there a quite a few in circulation now...
<chipb> oh. S5 would make sense too.
<chipb> that's pretty cool.